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From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Tim Kryger <tim.kryger@gmail.com>
Cc: Alan Cox <alan@linux.intel.com>,
	"long.wanglong" <long.wanglong@huawei.com>,
	Peter Hurley <peter@hurleysoftware.com>,
	Zhang Zhen <zhenzhang.zhang@huawei.com>,
	linux-serial@vger.kernel.org,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jamie Iles <jamie@jamieiles.com>, Arnd Bergmann <arnd@arndb.de>,
	shenjiangjiang@huawei.com, Wang Kai <morgan.wang@huawei.com>
Subject: Re: [RFC] With 8250 Designware UART, if writes to the LCR failed the kernel will hung up
Date: Fri, 13 Mar 2015 17:36:24 +0200	[thread overview]
Message-ID: <CAHp75Vd5UhG1nLfmLw3KgUjYsVi5JBq2=UZx1A=ec0Bu5htAMw@mail.gmail.com> (raw)
In-Reply-To: <CAD7vxx+WYgOujpTAxXsUmcr8T4zHS9MYfwrWu8hV2t=TudLamQ@mail.gmail.com>

On Tue, Mar 10, 2015 at 4:47 AM, Tim Kryger <tim.kryger@gmail.com> wrote:
> On Mon, Mar 9, 2015 at 8:05 AM, Alan Cox <alan@linux.intel.com> wrote:
>
>> Ah no - I meant what is their official software workaround for existing
>> parts with the bug ? Presumably they have an errata document that
>> discusses this and the correct methods they recommend to avoid the
>> hang ?
>
> As far as I know, the only advice they provided was rather naive.
>
> The documentation I saw suggested stashing a copy of the LCR and then
> rewriting it when the special LCR write failed interrupt was raised.
>
> That approach was not workable as the LCR might be written while the
> interrupt is masked causing the sequence of register writes to occur
> in an order other than what was desired.
>
> Additionally, when the LCR needed to be re-written but the UART stayed
> busy, the interrupt would keep firing and the driver would starve out
> everything else on the CPU.
>
> The current workaround of clearing fifos and retrying a fixed number
> of times isn't ideal but I'm not sure what else can be done given the
> way this hardware works.
>
> Additional background is in c49436b657d0a56a6ad90d14a7c3041add7cf64d

I hit the similar problem as Zhang described quite long ago when I
tried to write to the port chosen as console.
In my case seems the same (DW) IP is enumerated via PCI. Do we need to
tweak PCI cases as well?


-- 
With Best Regards,
Andy Shevchenko

  parent reply	other threads:[~2015-03-13 15:36 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-06  9:11 Zhang Zhen
2015-03-06 16:50 ` Peter Hurley
2015-03-07  3:01   ` Tim Kryger
2015-03-09  7:10     ` long.wanglong
2015-03-09 13:32       ` Alan Cox
2015-03-09 14:36         ` Tim Kryger
2015-03-09 15:05           ` Alan Cox
2015-03-10  2:47             ` Tim Kryger
2015-03-10  3:15               ` Zhang Zhen
2015-03-10 13:25               ` Peter Hurley
2015-03-11  1:20                 ` Zhang Zhen
2015-03-13 15:36               ` Andy Shevchenko [this message]
2015-03-15 14:50                 ` Peter Hurley

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