From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE296C432BE for ; Thu, 29 Jul 2021 03:15:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B579C60F9B for ; Thu, 29 Jul 2021 03:15:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233589AbhG2DPy (ORCPT ); Wed, 28 Jul 2021 23:15:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233555AbhG2DPw (ORCPT ); Wed, 28 Jul 2021 23:15:52 -0400 Received: from mail-il1-x131.google.com (mail-il1-x131.google.com [IPv6:2607:f8b0:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C672FC061757 for ; Wed, 28 Jul 2021 20:15:49 -0700 (PDT) Received: by mail-il1-x131.google.com with SMTP id q18so4299169ile.9 for ; Wed, 28 Jul 2021 20:15:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=GEHpVphhyLJFXCEe7iQRjsD/9tyMnPNRqVbPlXIwLE4=; b=H90NoVLKUmuE48C1hAsE0ENepOFZRurynbwu4Ws/QA1jGVRagWYAhHGiC8+m2XW69W JA9fHV1GqZL6fM7sH2FKKneMMmwqYPo8v4iPz8hoSF6djxgc3bXBfUay/zJ28wLYWvpT vkll/a6MvrPvAukm8GFHf+MXXIuhOKhN/2AKk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=GEHpVphhyLJFXCEe7iQRjsD/9tyMnPNRqVbPlXIwLE4=; b=NR/1CejzW6aZQFBsFHIq3KvqpoCEXv4iVVVgdVt1ZUT+To3fsIGZ1yJMNBPPJ2HrP5 zIOqqpKdgIcgwB6qfzEW9pQuQb9Q8BsxVxE/TVGQsmCuGwuHakmr1uCF2U0nkqueiE8O XASp+/CJliQSSPwJrGHNUJnMmrJ8v6xpKBxSXC/5zoC64eJsLp2thUclE7pKuW/EdOGc 2leHMYMU6Ykc7BTREyITSnL91Hoi7MKKL/COJ20TtCJrhD84gg2TWTzhWNZLvmXUb+Sg fpX6VFjIkigxm5jM2AglsYqWDuzILLYRV/w0xFw4coC8HqWTuSlz3drayP7WwR2ZIFzt 3xiQ== X-Gm-Message-State: AOAM531H8IWU5JXgaajVpJx3FNKsw0MLThW2Kr2KwFp2JrLbniL6F3my aRUxTaFDwx5zFiuCK/spMg3ZahAn7oHbW9A6E+7qAg== X-Google-Smtp-Source: ABdhPJyPsS75VPrbgercdilELkiuOWzRBn0SaHkomjCxnwrLSJus0YUdJJOv5CRdtmWxFFYOzx1hw2W2wQKSbbm/++c= X-Received: by 2002:a05:6e02:d8f:: with SMTP id i15mr2072719ilj.102.1627528549224; Wed, 28 Jul 2021 20:15:49 -0700 (PDT) MIME-Version: 1.0 References: <20210727174025.10552-1-linux@fw-web.de> In-Reply-To: <20210727174025.10552-1-linux@fw-web.de> From: Hsin-Yi Wang Date: Thu, 29 Jul 2021 11:15:23 +0800 Message-ID: Subject: Re: [PATCH] soc: mmsys: mediatek: add mask to mmsys routes To: Frank Wunderlich Cc: "moderated list:ARM/Mediatek SoC support" , CK Hu , Matthias Brugger , Enric Balletbo i Serra , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , lkml , stable@vger.kernel.org, Frank Wunderlich Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 28, 2021 at 1:41 AM Frank Wunderlich wrote: > > From: CK Hu > > SOUT has many bits and need to be cleared before set new value. > Write only could do the clear, but for MOUT, it clears bits that > should not be cleared. So use a mask to reset only the needed bits. > > this fixes HDMI issues on MT7623/BPI-R2 since 5.13 > > Cc: stable@vger.kernel.org > Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") > Signed-off-by: Frank Wunderlich > Signed-off-by: CK Hu > --- > code is taken from here (upstreamed without mask part) > https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2345186/5 > basicly CK Hu's code so i set him as author > --- > drivers/soc/mediatek/mtk-mmsys.c | 7 +- > drivers/soc/mediatek/mtk-mmsys.h | 133 +++++++++++++++++++++---------- > 2 files changed, 98 insertions(+), 42 deletions(-) > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 080660ef11bf..0f949896fd06 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -68,7 +68,9 @@ void mtk_mmsys_ddp_connect(struct device *dev, > > for (i = 0; i < mmsys->data->num_routes; i++) > if (cur == routes[i].from_comp && next == routes[i].to_comp) { > - reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val; > + reg = readl_relaxed(mmsys->regs + routes[i].addr); > + reg &= ~routes[i].mask; > + reg |= routes[i].val; > writel_relaxed(reg, mmsys->regs + routes[i].addr); > } > } > @@ -85,7 +87,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > > for (i = 0; i < mmsys->data->num_routes; i++) > if (cur == routes[i].from_comp && next == routes[i].to_comp) { > - reg = readl_relaxed(mmsys->regs + routes[i].addr) & ~routes[i].val; > + reg = readl_relaxed(mmsys->regs + routes[i].addr); > + reg &= ~routes[i].mask; This patch is breaking the mt8183 internal display. I think it's because ~routes[i].val; is removed? Also what should the routes[i].mask be if it's not set in mmsys_mt8183_routing_table? > writel_relaxed(reg, mmsys->regs + routes[i].addr); > } > }