From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 582D1C432BE for ; Thu, 29 Jul 2021 05:47:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 39B4361052 for ; Thu, 29 Jul 2021 05:47:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233997AbhG2Fre (ORCPT ); Thu, 29 Jul 2021 01:47:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233899AbhG2Frc (ORCPT ); Thu, 29 Jul 2021 01:47:32 -0400 Received: from mail-io1-xd2d.google.com (mail-io1-xd2d.google.com [IPv6:2607:f8b0:4864:20::d2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC5AEC061765 for ; Wed, 28 Jul 2021 22:47:29 -0700 (PDT) Received: by mail-io1-xd2d.google.com with SMTP id n19so5626267ioz.0 for ; Wed, 28 Jul 2021 22:47:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=w60/VELNDBnq6j43CmiV7Bx6nr6aPzyLJ2Noe+SivnU=; b=VuKnsO+XEmpG5oBRxRnV4vci8jUzDUJaY8oLacnkFTs1pQJf9EeWbGzarIi36gyTGd k+v0GMNZu+INYDyKSbwqC0mWrmrBLymIDpOOpIehPCXQ+Y6ZwbKBHsX3YbQBbhnfE4zP PQ8bi7V7Pf6pIxuHsl9EvhHrpPp6J5iaO9/Ec= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=w60/VELNDBnq6j43CmiV7Bx6nr6aPzyLJ2Noe+SivnU=; b=RxSoMt73Y+15FUrJwMrGAhG1ykWFacbmhwGXhM+tbDV7453KAzpVR4fu3X8VuqMutH GY9ww+55qgpSHh8vGeA+zCRIDpWCFlangyGwObs2gjA6Wl2w9RrXrVnlHxE3x1o91//T f3IsH+Wv512np5gypQC+tUx7y9oNUwIAwoiO5FQp70VMV3cZvfmO10YsCc+Rxkp/YfMJ z2ZN12RpAL9IKfzD3dQMGXJaGcZM2S4/fWqdWpcTArIl5vqS+sLxCuyU4GWA34dbd/r7 h6CI8coE6mkvY2ftiZeVb9oQZ0ylOOGGETpLOstOoEcHzdgZjHriS4sMdpFZW9yGanCC gBNA== X-Gm-Message-State: AOAM533LaiPTFss5YxSVJyr6+9O9KFRQaFOdNjMpN8pKz90uRT9VXNYo qWWYwzOTZgj8ILyPSmmVLZSUd5H55phoogt8tOo7lwWHFkokqg== X-Google-Smtp-Source: ABdhPJwsKcPUZyLkIjwGaAUj8BpR75Su46CVaCo58W4CpPpfcjnsCOLGplNVhzoC+fkaqbXezwlnNhfwrLpJ1BoHuSs= X-Received: by 2002:a02:6946:: with SMTP id e67mr3016189jac.4.1627537649171; Wed, 28 Jul 2021 22:47:29 -0700 (PDT) MIME-Version: 1.0 References: <20210727174025.10552-1-linux@fw-web.de> <97C4FA94-B28A-4F0E-9CD3-4E33B01BA353@fw-web.de> In-Reply-To: <97C4FA94-B28A-4F0E-9CD3-4E33B01BA353@fw-web.de> From: Hsin-Yi Wang Date: Thu, 29 Jul 2021 13:47:03 +0800 Message-ID: Subject: Re: [PATCH] soc: mmsys: mediatek: add mask to mmsys routes To: Frank Wunderlich Cc: "moderated list:ARM/Mediatek SoC support" , CK Hu , Matthias Brugger , Enric Balletbo i Serra , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , lkml , stable@vger.kernel.org, Frank Wunderlich Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 29, 2021 at 1:40 PM Frank Wunderlich wrote: > > Am 29. Juli 2021 05:15:23 MESZ schrieb Hsin-Yi Wang : > > >This patch is breaking the mt8183 internal display. I think it's > >because ~routes[i].val; is removed? > >Also what should the routes[i].mask be if it's not set in > >mmsys_mt8183_routing_table? > > > >> writel_relaxed(reg, mmsys->regs + > >routes[i].addr); > >> } > >> } > > > > The mask should reset the needed bits,maybe it needs to be adjusted for your ddp components... > > Can you add some debugs inside loops in mtk_mmsys_ddp_connect and mtk_mmsys_ddp_disconnect (show read val,mask and final mask before write) to show differences before and after the patch? > struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; u32 addr; + u32 mask; u32 val; }; mask is not the last element, and mmsys_mt8183_routing_table = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L } ... so the mask and val will be wrong. CK, do you know what mask we should set for mt8183? Or can we just set a dummy 0 mask. > regards Frank