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From: Rob Herring <robh@kernel.org>
To: Jolly Shah <JOLLYS@xilinx.com>
Cc: "mturquette@baylibre.com" <mturquette@baylibre.com>,
	"sboyd@codeaurora.org" <sboyd@codeaurora.org>,
	"michal.simek@xilinx.com" <michal.simek@xilinx.com>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Shubhrajyoti Datta <shubhraj@xilinx.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Rajan Vaja <RAJANV@xilinx.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/3] dt-bindings: clock: Add bindings for ZynqMP clock driver
Date: Wed, 7 Mar 2018 19:20:00 -0600	[thread overview]
Message-ID: <CAL_JsqKUC47xB5O2Y6c3efVCjJY=V+XO3xyLTU9rNia40bdZkg@mail.gmail.com> (raw)
In-Reply-To: <DM2PR0201MB0767031248A9F773620722FDB8D80@DM2PR0201MB0767.namprd02.prod.outlook.com>

On Wed, Mar 7, 2018 at 4:47 PM, Jolly Shah <JOLLYS@xilinx.com> wrote:
> Hi Rob,
>
>
>> -----Original Message-----
>> From: Rob Herring [mailto:robh@kernel.org]
>> Sent: Monday, March 05, 2018 5:46 PM
>> To: Jolly Shah <JOLLYS@xilinx.com>
>> Cc: mturquette@baylibre.com; sboyd@codeaurora.org;
>> michal.simek@xilinx.com; mark.rutland@arm.com; linux-clk@vger.kernel.org;
>> devicetree@vger.kernel.org; Shubhrajyoti Datta <shubhraj@xilinx.com>; linux-
>> kernel@vger.kernel.org; Jolly Shah <JOLLYS@xilinx.com>; Rajan Vaja
>> <RAJANV@xilinx.com>; linux-arm-kernel@lists.infradead.org
>> Subject: Re: [PATCH 2/3] dt-bindings: clock: Add bindings for ZynqMP clock
>> driver
>>
>> On Wed, Feb 28, 2018 at 02:27:40PM -0800, Jolly Shah wrote:
>> > Add documentation to describe Xilinx ZynqMP clock driver bindings.
>> >
>> > Signed-off-by: Jolly Shah <jollys@xilinx.com>
>> > Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
>> > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
>> > ---

>> > +95         dpll_post_src
>> > +96         vpll_int
>> > +97         vpll_pre_src
>> > +98         vpll_half
>> > +99         vpll_int_mux
>> > +100                vpll_post_src
>> > +101                can0_mio
>> > +102                can1_mio
>> > +
>> > +Example:
>> > +
>> > +clk: clk {
>> > +   #clock-cells = <1>;
>> > +   compatible = "xlnx,zynqmp-clk";
>>
>> How do you control the clocks?
>
> Clocks are controlled by a dedicated platform management controller. Above clock ids are used to identify clocks between master and PMU.

What is the interface to the "platform management controller"? Because
you have no registers, I'm guessing a firmware interface? If so, then
just define the firmware node as a clock provider.

Rob

  reply	other threads:[~2018-03-08  1:20 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-28 22:27 [PATCH 0/3] drivers: clk: Add ZynqMp clock driver support Jolly Shah
2018-02-28 22:27 ` [PATCH 1/3] drivers: clk: Add clk_get_children support Jolly Shah
2018-03-19 18:21   ` Stephen Boyd
2018-03-20 19:29     ` Jolly Shah
2018-02-28 22:27 ` [PATCH 2/3] dt-bindings: clock: Add bindings for ZynqMP clock driver Jolly Shah
2018-03-06  1:45   ` Rob Herring
2018-03-07 22:47     ` Jolly Shah
2018-03-08  1:20       ` Rob Herring [this message]
2018-03-13 18:39         ` Jolly Shah
2018-03-19 18:23           ` Stephen Boyd
2018-03-20 19:15             ` Jolly Shah
2018-02-28 22:27 ` [PATCH 3/3] drivers: clk: Add " Jolly Shah
2018-03-03  3:32   ` kbuild test robot
2018-03-05 10:37     ` Sudeep Holla
2018-03-19 20:09   ` Stephen Boyd
2018-03-21 19:59     ` Jolly Shah

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