Re: [PATCH v2 2/3] phy/rockchip: add naneng combo phy for RK3568

[Peter Geis <pgwipeout@gmail.com>]

On Fri, Oct 22, 2021 at 6:51 AM Vinod Koul <vkoul@kernel.org> wrote:
>
> On 13-10-21, 18:19, Yifeng Zhao wrote:
> > This patch implements a combo phy driver for Rockchip SoCs
> > with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
> > sata-phy or sgmii-phy.
> >
> > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> > ---
> >
> > Changes in v2:
> > - Using api devm_platform_get_and_ioremap_resource.
> > - Modify rockchip_combphy_set_Mode.
> > - Add some PHY registers definition.
> >
> >  drivers/phy/rockchip/Kconfig                  |   8 +
> >  drivers/phy/rockchip/Makefile                 |   1 +
> >  .../rockchip/phy-rockchip-naneng-combphy.c    | 650 ++++++++++++++++++
> >  3 files changed, 659 insertions(+)
> >  create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> >
> > diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> > index e812adad7242..9022e395c056 100644
> > --- a/drivers/phy/rockchip/Kconfig
> > +++ b/drivers/phy/rockchip/Kconfig
> > @@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
> >         Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
> >         Innosilicon IP block.
> >
> > +config PHY_ROCKCHIP_NANENG_COMBO_PHY
> > +     tristate "Rockchip NANENG COMBO PHY Driver"
> > +     depends on ARCH_ROCKCHIP && OF
> > +     select GENERIC_PHY
> > +     help
> > +       Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
> > +       combo PHY with NaNeng IP block.
> > +
> >  config PHY_ROCKCHIP_PCIE
> >       tristate "Rockchip PCIe PHY Driver"
> >       depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
> > diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> > index f0eec212b2aa..a5041efb5b8f 100644
> > --- a/drivers/phy/rockchip/Makefile
> > +++ b/drivers/phy/rockchip/Makefile
> > @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)       += phy-rockchip-inno-csidphy.o
> >  obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)      += phy-rockchip-inno-dsidphy.o
> >  obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
> >  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
> > +obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY)  += phy-rockchip-naneng-combphy.o
> >  obj-$(CONFIG_PHY_ROCKCHIP_PCIE)              += phy-rockchip-pcie.o
> >  obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)     += phy-rockchip-typec.o
> >  obj-$(CONFIG_PHY_ROCKCHIP_USB)               += phy-rockchip-usb.o
> > diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> > new file mode 100644
> > index 000000000000..fbfc5fbbd5b8
> > --- /dev/null
> > +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> > @@ -0,0 +1,650 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Rockchip PIPE USB3.0 PCIE SATA combphy driver
> > + *
> > + * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +#include <linux/reset.h>
> > +#include <dt-bindings/phy/phy.h>
> > +
> > +#define BIT_WRITEABLE_SHIFT          16
> > +#define REF_CLOCK_24MHz                      24000000
> > +#define REF_CLOCK_25MHz                      25000000
> > +#define REF_CLOCK_100MHz             100000000
> > +/* RK3568 T22 COMBO PHY REG */
> > +#define RK3568_T22_PHYREG5           (0x5 << 2)
> > +#define T22_PHYREG5_PLL_DIV_MASK     GENMASK(7, 6)
> > +#define T22_PHYREG5_PLL_DIV_SHIFT    6
> > +#define T22_PHYREG5_PLL_DIV_2                1
> > +
> > +#define RK3568_T22_PHYREG6           (0x6 << 2)
> > +#define T22_PHYREG6_TX_RTERM_MASK    GENMASK(7, 4)
> > +#define T22_PHYREG6_TX_RTERM_SHIFT   4
> > +#define T22_PHYREG6_TX_RTERM_50OHM   0x8
> > +#define T22_PHYREG6_RX_RTERM_MASK    GENMASK(3, 0)
> > +#define T22_PHYREG6_RX_RTERM_SHIFT   0
> > +#define T22_PHYREG6_RX_RTERM_44OHM   0xF
> > +
> > +#define RK3568_T22_PHYREG7           (0x7 << 2)
>
> Pls use GENMASK for these?
>
> > +#define T22_PHYREG7_SSC_EN           BIT(4)
> > +
> > +#define RK3568_T22_PHYREG10          (0xA << 2)
> > +#define T22_PHYREG10_SU_TRIM_0_7     0xF0
> > +
> > +#define RK3568_T22_PHYREG11          (0xB << 2)
> > +#define T22_PHYREG11_PLL_LPF_ADJ     0x4
> > +
> > +#define RK3568_T22_PHYREG12          (0xC << 2)
> > +#define T22_PHYREG12_RESISTER_MASK   GENMASK(5, 4)
> > +#define T22_PHYREG12_RESISTER_SHIFT  0x4
>
> bitfield.h has nice helpers which can extract/program values and avoid
> one to define these shifts

They aren't values, they are registers.
This is a remnant from the downstream driver's attempt at obfuscating
the register it's touching.
Please define these correctly.

> --
> ~Vinod
>
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