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From: Magnus Damm <magnus.damm@gmail.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Simon Horman <horms@verge.net.au>,
	SH-Linux <linux-sh@vger.kernel.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>
Subject: Re: [PATCH 02/02] ARM: shmobile: marzen-reference: Remove IRLM workaround
Date: Thu, 4 Dec 2014 18:24:32 +0900	[thread overview]
Message-ID: <CANqRtoQM8jrggMT7QFTQ1_1fKJgankkrUnF-wO8mJx3NqjxMTQ@mail.gmail.com> (raw)
In-Reply-To: <CAMuHMdW=-yXKUKQPc2rU0P2PQgjqnYzSZxZCPXLVYJjai+L04w@mail.gmail.com>

Hi Geert,

On Thu, Dec 4, 2014 at 6:19 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Hi Magnus,
>
> On Thu, Dec 4, 2014 at 8:33 AM, Magnus Damm <magnus.damm@gmail.com> wrote:
>>>> --- 0002/arch/arm/boot/dts/r8a7779.dtsi
>>>> +++ work/arch/arm/boot/dts/r8a7779.dtsi       2014-12-03 20:27:49.000000000 +0900
>>>> @@ -139,7 +139,7 @@
>>>>               interrupt-controller;
>>>>       };
>>>>
>>>> -     irqpin0: irqpin@fe780010 {
>>>> +     irqpin0: irqpin@fe780000 {
>>>>               compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
>>>>               #interrupt-cells = <2>;
>>>>               status = "disabled";
>>>> @@ -148,7 +148,8 @@
>>>>                       <0xfe780010 4>,
>>>>                       <0xfe780024 4>,
>>>>                       <0xfe780044 4>,
>>>> -                     <0xfe780064 4>;
>>>> +                     <0xfe780064 4>,
>>>> +                     <0xfe780000 4>;
>>>
>>> Is there any order implied by the above list?
>>> Naïvely I would expect it to be sorted numerically.
>>
>> Yes, the driver assumes the register banks to be passed in a certain
>> order. In the case of r8a7779 we add one more register bank at the end
>> for IRLM setup. Register detail (base address, access size, order and
>> bitfield width) varies with SoC version. So the IRLM register will be
>> at different addresses depending on SoC, but the driver wants it at
>> the end of the list.
>
> As these are all individual registers, and there are that many, I think
> it's worth adding a reg-names property to identify the registers.
> Of course the driver still has to support the old anonymous order
> for backwards compatibility.

If we should rework things, then I propose going the other way around.
=) Basically only passing a single base address with a certain SoC
specific compat string, and based on that letting the driver
internally figure out which register is at what offset and the access
size and bitfield size. Either way we have a limited number of SoCs
and they are all old.

Cheers,

/ magnus

  reply	other threads:[~2014-12-04  9:24 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-12-03 12:17 [PATCH 00/02] r8a7779 renesas-intc-irqpin IRLM configuration patches Magnus Damm
2014-12-03 12:18 ` [PATCH 01/02] irqchip: renesas-intc-irqpin: r8a7779 IRLM setup support Magnus Damm
2014-12-04  7:18   ` Simon Horman
2014-12-04  7:29     ` Magnus Damm
2014-12-04  7:51       ` Simon Horman
2015-01-26 10:43   ` [tip:irq/core] " tip-bot for Magnus Damm
2014-12-03 12:18 ` [PATCH 02/02] ARM: shmobile: marzen-reference: Remove IRLM workaround Magnus Damm
2014-12-04  7:21   ` Simon Horman
2014-12-04  7:33     ` Magnus Damm
2014-12-04  7:52       ` Simon Horman
2014-12-04  9:19       ` Geert Uytterhoeven
2014-12-04  9:24         ` Magnus Damm [this message]
2014-12-04  9:31           ` Geert Uytterhoeven
2014-12-04 10:20             ` Magnus Damm

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