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From: Magnus Damm <magnus.damm@gmail.com>
To: Simon Horman <horms@verge.net.au>
Cc: SH-Linux <linux-sh@vger.kernel.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>
Subject: Re: [PATCH 02/02] ARM: shmobile: marzen-reference: Remove IRLM workaround
Date: Thu, 4 Dec 2014 16:33:25 +0900	[thread overview]
Message-ID: <CANqRtoRq5j6q=XGd1eJUH5TzSAGmZjyxnnSs+p_jum50zZn0Wg@mail.gmail.com> (raw)
In-Reply-To: <20141204072153.GE25806@verge.net.au>

Hi Simon,

On Thu, Dec 4, 2014 at 4:21 PM, Simon Horman <horms@verge.net.au> wrote:
> Hi Magnus,
>
> On Wed, Dec 03, 2014 at 09:18:13PM +0900, Magnus Damm wrote:
>> From: Magnus Damm <damm+renesas@opensource.se>
>>
>> Adjust the r8a7779 SoC DTS and the Marzen Reference
>> C board code to use DTS only for INTC-IRQPIN IRLM setup.
>>
>> Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
>> ---
>>
>>  Written on top of renesas-devel-20141202-v3.18-rc7 and
>>  [PATCH] ARM: shmobile: r8a7779 CCF DTS update
>>
>>  Has a runtime dependency on:
>>  [PATCH 01/02] irqchip: renesas-intc-irqpin: r8a7779 IRLM setup support
>>
>>  arch/arm/boot/dts/r8a7779.dtsi                  |    5 +++--
>>  arch/arm/mach-shmobile/board-marzen-reference.c |    7 -------
>>  2 files changed, 3 insertions(+), 9 deletions(-)
>>
>> --- 0002/arch/arm/boot/dts/r8a7779.dtsi
>> +++ work/arch/arm/boot/dts/r8a7779.dtsi       2014-12-03 20:27:49.000000000 +0900
>> @@ -139,7 +139,7 @@
>>               interrupt-controller;
>>       };
>>
>> -     irqpin0: irqpin@fe780010 {
>> +     irqpin0: irqpin@fe780000 {
>>               compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
>>               #interrupt-cells = <2>;
>>               status = "disabled";
>> @@ -148,7 +148,8 @@
>>                       <0xfe780010 4>,
>>                       <0xfe780024 4>,
>>                       <0xfe780044 4>,
>> -                     <0xfe780064 4>;
>> +                     <0xfe780064 4>,
>> +                     <0xfe780000 4>;
>
> Is there any order implied by the above list?
> Naïvely I would expect it to be sorted numerically.

Yes, the driver assumes the register banks to be passed in a certain
order. In the case of r8a7779 we add one more register bank at the end
for IRLM setup. Register detail (base address, access size, order and
bitfield width) varies with SoC version. So the IRLM register will be
at different addresses depending on SoC, but the driver wants it at
the end of the list.

Cheers,

/ magnus

  reply	other threads:[~2014-12-04  7:33 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-12-03 12:17 [PATCH 00/02] r8a7779 renesas-intc-irqpin IRLM configuration patches Magnus Damm
2014-12-03 12:18 ` [PATCH 01/02] irqchip: renesas-intc-irqpin: r8a7779 IRLM setup support Magnus Damm
2014-12-04  7:18   ` Simon Horman
2014-12-04  7:29     ` Magnus Damm
2014-12-04  7:51       ` Simon Horman
2015-01-26 10:43   ` [tip:irq/core] " tip-bot for Magnus Damm
2014-12-03 12:18 ` [PATCH 02/02] ARM: shmobile: marzen-reference: Remove IRLM workaround Magnus Damm
2014-12-04  7:21   ` Simon Horman
2014-12-04  7:33     ` Magnus Damm [this message]
2014-12-04  7:52       ` Simon Horman
2014-12-04  9:19       ` Geert Uytterhoeven
2014-12-04  9:24         ` Magnus Damm
2014-12-04  9:31           ` Geert Uytterhoeven
2014-12-04 10:20             ` Magnus Damm

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