From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754895AbeDTNFV (ORCPT ); Fri, 20 Apr 2018 09:05:21 -0400 Received: from mail-sn1nam01on0078.outbound.protection.outlook.com ([104.47.32.78]:42330 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754769AbeDTNFT (ORCPT ); Fri, 20 Apr 2018 09:05:19 -0400 From: "Ghannam, Yazen" To: Borislav Petkov CC: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "tony.luck@intel.com" , "x86@kernel.org" Subject: RE: [PATCH] x86/MCE, EDAC/mce_amd: Save all aux registers on SMCA systems Thread-Topic: [PATCH] x86/MCE, EDAC/mce_amd: Save all aux registers on SMCA systems Thread-Index: AQHTyrzRqCN7fg42eUKg23bN8kMvXKQFS3EAgAAGZOCAAYnqgIAC2dNg Date: Fri, 20 Apr 2018 13:05:17 +0000 Message-ID: References: <20180402195707.42875-1-Yazen.Ghannam@amd.com> <20180417172102.GA3633@pd.tnic> <20180418171347.GH4795@pd.tnic> In-Reply-To: <20180418171347.GH4795@pd.tnic> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: alien8.de; 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x-microsoft-antispam-message-info: 6fyZ5+wljIYede1cKzqWr9VQ/wGnEo8CNaYP2pc+3GgZY0mJSo2vegk1Hn/MwoTz42/aHcjBPnrLiclMw29HWHuVqD5exG+Cpm879IILUVOM1SEU2lBdbcZZcaYInYHa4V+WUwC6yfzaI5tJ3h34Dzi2lKPI0TLW0CUWpoWiEUj1ntGZuiXHd/fgJQcI3zuB spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 5844cae3-16b8-40c2-9324-08d5a6bf5d55 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5844cae3-16b8-40c2-9324-08d5a6bf5d55 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Apr 2018 13:05:17.6084 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1413 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w3KD5QqC024457 > -----Original Message----- > From: Borislav Petkov > Sent: Wednesday, April 18, 2018 1:14 PM > To: Ghannam, Yazen > Cc: linux-edac@vger.kernel.org; linux-kernel@vger.kernel.org; > tony.luck@intel.com; x86@kernel.org > Subject: Re: [PATCH] x86/MCE, EDAC/mce_amd: Save all aux registers on > SMCA systems > > On Tue, Apr 17, 2018 at 06:30:34PM +0000, Ghannam, Yazen wrote: > > We could but it's an issue of documentation and testing the older systems. > > > > My first pass at this was to unconditionally read the registers because my > > understanding was that registers that aren't accessible would be read-as- > zero. > > I thought this was a common MCA implementation. But Tony pointed out > that > > this isn't the case on Intel systems. This is the case on recent AMD systems. > But > > I don't know if it's the case on older systems which may or may not have > > followed the Intel implementation more closely. > > So if our worry is the #GPs, we can always use the rdmsr*_safe() > variants and look at the return value. And dump a invalid value like > 0xdeadbeef or so, if the read failed. > > But if any bit of info we've gotten this way, helps us debug an MCE, > we're already golden! > Okay, I can do that. What about using mce_rdmsrl()? The value gets set to 0 and a user gets a single warning. This may be more clear to the user. Also, it shouldn't affect code that checks for non-zero values, like in __print_mce(). > > For example, > > > > Deferred error occurs: > > - MCA_{STATUS,ADDR,DESTAT,DEADDR} all have valid data. > > > > MCE occurs > > - MCA_{STATUS,ADDR} are overwritten with non-zero data. > > - MCE handler clears MCA_STATUS. MCA_ADDR is non-zero. > > > > DFR handler finds MCA_STATUS[Deferred] is clear, so it saves > > MCA_DESTAT and MCA_DEADDR which is 0. > > > > If !m->addr (which has MCA_DEADDR), then we read MCA_STATUS > > which has the address from the MCE. > > The code could use a shorter version of this as a comment to state why > we're doing it. Because it is not obvious. > Yes, will do. Thanks, Yazen