LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
From: Vinod Koul <vkoul@kernel.org>
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>,
sbillaka@codeaurora.org, Rob Clark <robdclark@gmail.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Stephen Boyd <swboyd@chromium.org>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] phy: qcom: Introduce new eDP PHY driver
Date: Fri, 14 May 2021 16:10:21 +0530 [thread overview]
Message-ID: <YJ5TlcwcxV4E+jyh@vkoul-mobl.Dlink> (raw)
In-Reply-To: <20210511041930.592483-2-bjorn.andersson@linaro.org>
On 10-05-21, 23:19, Bjorn Andersson wrote:
> +static int qcom_edp_phy_power_on(struct phy *phy)
> +{
> + struct qcom_edp *edp = phy_get_drvdata(phy);
> + int timeout;
> + int ret;
> + u32 val;
> +
> + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
> + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN |
> + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
> + edp->edp + DP_PHY_PD_CTL);
> + writel(0xfc, edp->edp + DP_PHY_MODE);
> +
> + timeout = readl_poll_timeout(edp->pll + QSERDES_COM_CMN_STATUS,
> + val, val & BIT(7), 5, 200);
> + if (timeout)
> + return timeout;
> +
> + writel(0x01, edp->tx0 + TXn_LDO_CONFIG);
> + writel(0x01, edp->tx1 + TXn_LDO_CONFIG);
> + writel(0x00, edp->tx0 + TXn_LANE_MODE_1);
> + writel(0x00, edp->tx1 + TXn_LANE_MODE_1);
> +
> + ret = qcom_edp_configure_ssc(edp);
> + if (ret)
> + return ret;
> +
> + ret = qcom_edp_configure_pll(edp);
> + if (ret)
> + return ret;
> +
> + /* TX Lane configuration */
> + writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL);
> + writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL);
> +
> + /* TX-0 register configuration */
> + writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);
> + writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE);
> + writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN);
> + writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN);
> + writel(0x04, edp->tx0 + TXn_TX_BAND);
> +
> + /* TX-1 register configuration */
> + writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);
> + writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE);
> + writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN);
> + writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN);
> + writel(0x04, edp->tx1 + TXn_TX_BAND);
> +
> + ret = qcom_edp_set_vco_div(edp);
> + if (ret)
> + return ret;
> +
> + writel(0x01, edp->edp + DP_PHY_CFG);
> + writel(0x05, edp->edp + DP_PHY_CFG);
> + writel(0x01, edp->edp + DP_PHY_CFG);
> + writel(0x09, edp->edp + DP_PHY_CFG);
> +
> + writel(0x20, edp->pll + QSERDES_COM_RESETSM_CNTRL);
> +
> + timeout = readl_poll_timeout(edp->pll + QSERDES_COM_C_READY_STATUS,
> + val, val & BIT(0), 500, 10000);
> + if (timeout)
> + return timeout;
> +
> + writel(0x19, edp->edp + DP_PHY_CFG);
> + writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN);
> + writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN);
> + writel(0x00, edp->tx0 + TXn_TX_POL_INV);
> + writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN);
> + writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN);
> + writel(0x00, edp->tx1 + TXn_TX_POL_INV);
> + writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET);
> + writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET);
> + writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0);
> + writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1);
> + writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0);
> + writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1);
> +
> + writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL);
> + writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL);
> + writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL);
> + writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL);
> +
> + writel(0x4, edp->tx0 + TXn_HIGHZ_DRVR_EN);
> + writel(0x3, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN);
> + writel(0x4, edp->tx1 + TXn_HIGHZ_DRVR_EN);
> + writel(0x0, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN);
> + writel(0x3, edp->edp + DP_PHY_CFG_1);
> +
> + writel(0x18, edp->edp + DP_PHY_CFG);
Can't help but think that this should be made modular. We would come up
with next set which would have different set of sequence/values so
having a qmp style table here would be better..
--
~Vinod
next prev parent reply other threads:[~2021-05-14 10:40 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-11 4:19 [PATCH 1/2] dt-bindings: phy: Introduce Qualcomm eDP/DP PHY binding Bjorn Andersson
2021-05-11 4:19 ` [PATCH 2/2] phy: qcom: Introduce new eDP PHY driver Bjorn Andersson
2021-05-11 5:22 ` Stephen Boyd
2021-05-14 10:38 ` Vinod Koul
2021-05-11 14:24 ` Jeffrey Hugo
2021-05-11 14:46 ` Dmitry Baryshkov
2021-05-14 10:40 ` Vinod Koul [this message]
2021-08-10 3:15 ` sbillaka
2021-08-10 3:36 ` Bjorn Andersson
2021-08-12 0:23 ` sbillaka
2021-05-11 17:24 ` [PATCH 1/2] dt-bindings: phy: Introduce Qualcomm eDP/DP PHY binding Stephen Boyd
2021-05-17 21:46 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YJ5TlcwcxV4E+jyh@vkoul-mobl.Dlink \
--to=vkoul@kernel.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=kishon@ti.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=robdclark@gmail.com \
--cc=robh+dt@kernel.org \
--cc=sbillaka@codeaurora.org \
--cc=swboyd@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).