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From: Vinod Koul <vkoul@kernel.org>
To: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	linuxarm@huawei.com, mauro.chehab@huawei.com,
	Rob Herring <robh@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Manivannan Sadhasivam <mani@kernel.org>,
	linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH v9 01/11] phy: HiSilicon: Add driver for Kirin 970 PCIe PHY
Date: Fri, 6 Aug 2021 18:47:37 +0530	[thread overview]
Message-ID: <YQ02cc1dtqQBlT4/@matsya> (raw)
In-Reply-To: <90aada2f51b58c162e199faf823ba887e50f1dc6.1628092716.git.mchehab+huawei@kernel.org>

On 04-08-21, 18:02, Mauro Carvalho Chehab wrote:

> +/* define ie,oe cfg */
> +#define IO_IE_EN_HARD_BYPASS         (0x1 << 27)
> +#define IO_OE_EN_HARD_BYPASS         (0x1 << 11)
> +#define IO_HARD_CTRL_DEBOUNCE_BYPASS (0x1 << 10)
> +#define IO_OE_GT_MODE                (0x2 << 7)
> +#define DEBOUNCE_WAITCFG_IN          (0xf << 20)
> +#define DEBOUNCE_WAITCFG_OUT         (0xf << 13)

Why not use BIT() or GENMASK for these?

> +/* Registers in PCIePHY */
> +static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy,
> +					 u32 val, u32 reg)
> +{
> +	writel(val, phy->base + 0x40000 + reg);

magic 0x40000?

> +}
> +
> +static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg)
> +{
> +	return readl(phy->base + 0x40000 + reg);
> +}
> +
> +static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy,
> +						u32 val, u32 reg)
> +{
> +	writel(val, phy->base + reg * 4);

why * 4 ..?

> +static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)
> +{
> +	u32 val;
> +
> +	val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
> +
> +	if (phy->eye_param[1] != EYEPARAM_NOCFG) {
> +		val &= (~0xf00);
> +		val |= (phy->eye_param[1] << 8) | (0x1 << 12);
> +	}

again too many magic numbers, Do check FIELD_GET/PREP macros for these?
-- 
~Vinod

  reply	other threads:[~2021-08-06 13:17 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-04 16:02 [PATCH v9 00/11] Add support for Hikey 970 PCIe Mauro Carvalho Chehab
2021-08-04 16:02 ` [PATCH v9 01/11] phy: HiSilicon: Add driver for Kirin 970 PCIe PHY Mauro Carvalho Chehab
2021-08-06 13:17   ` Vinod Koul [this message]
2021-08-04 16:02 ` [PATCH v9 02/11] PCI: kirin: Reorganize the PHY logic inside the driver Mauro Carvalho Chehab
2021-08-04 16:02 ` [PATCH v9 03/11] PCI: kirin: Add support for a PHY layer Mauro Carvalho Chehab
2021-08-04 16:03 ` [PATCH v9 04/11] PCI: kirin: Use regmap for APB registers Mauro Carvalho Chehab
2021-08-04 16:03 ` [PATCH v9 05/11] PCI: kirin: Add support for bridge slot DT schema Mauro Carvalho Chehab
2021-08-04 16:03 ` [PATCH v9 06/11] PCI: kirin: Add Kirin 970 compatible Mauro Carvalho Chehab
2021-08-04 16:03 ` [PATCH v9 07/11] PCI: kirin: Add MODULE_* macros Mauro Carvalho Chehab
2021-08-04 16:03 ` [PATCH v9 08/11] PCI: kirin: Allow building it as a module Mauro Carvalho Chehab
2021-08-04 16:03 ` [PATCH v9 09/11] PCI: kirin: Add power_off support for Kirin 960 PHY Mauro Carvalho Chehab
2021-08-04 16:03 ` [PATCH v9 10/11] PCI: kirin: fix poweroff sequence Mauro Carvalho Chehab
2021-08-04 16:03 ` [PATCH v9 11/11] PCI: kirin: Allow removing the driver Mauro Carvalho Chehab

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