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From: Sean Christopherson <seanjc@google.com>
To: Wei Huang <wei.huang2@amd.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	pbonzini@redhat.com, vkuznets@redhat.com, wanpengli@tencent.com,
	jmattson@google.com, joro@8bytes.org, tglx@linutronix.de,
	mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com
Subject: Re: [PATCH v3 3/3] KVM: SVM: Add 5-level page table support for SVM
Date: Wed, 18 Aug 2021 17:32:44 +0000	[thread overview]
Message-ID: <YR1EPNRNtIZZ7LXd@google.com> (raw)
In-Reply-To: <20210818165549.3771014-4-wei.huang2@amd.com>

On Wed, Aug 18, 2021, Wei Huang wrote:
> When the 5-level page table is enabled on host OS, the nested page table
> for guest VMs must use 5-level as well. Update get_npt_level() function
> to reflect this requirement. In the meanwhile, remove the code that
> prevents kvm-amd driver from being loaded when 5-level page table is
> detected.
> 
> Signed-off-by: Wei Huang <wei.huang2@amd.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

If this patch authored by Paolo, he needs to be attributed via From:.  If Paolo
is a co-author, he needs a Co-developed-by:.  If either of those is true, your
SOB needs to be last in the chain since you are the last handler of the patch.
If neither is true, Paolo's SOB should be removed.

> ---
>  arch/x86/kvm/svm/svm.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> index b34840a2ffa7..ecc4bb8e4ea0 100644
> --- a/arch/x86/kvm/svm/svm.c
> +++ b/arch/x86/kvm/svm/svm.c
> @@ -261,7 +261,9 @@ u32 svm_msrpm_offset(u32 msr)
>  static int get_max_npt_level(void)
>  {
>  #ifdef CONFIG_X86_64
> -	return PT64_ROOT_4LEVEL;
> +	bool la57 = (cr4_read_shadow() & X86_CR4_LA57) != 0;
> +
> +	return la57 ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;

Why obfuscate this?  KVM is completely hosed if pgtable_l5_enabled() doesn't
match host CR4.  E.g.

	return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;

>  #else
>  	return PT32E_ROOT_LEVEL;
>  #endif
> @@ -462,11 +464,6 @@ static int has_svm(void)
>  		return 0;
>  	}
>  
> -	if (pgtable_l5_enabled()) {
> -		pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n");
> -		return 0;
> -	}
> -
>  	return 1;
>  }
>  
> -- 
> 2.31.1
> 

  reply	other threads:[~2021-08-18 17:32 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-18 16:55 [PATCH v3 0/3] SVM 5-level page table support Wei Huang
2021-08-18 16:55 ` [PATCH v3 1/3] KVM: x86: Allow CPU to force vendor-specific TDP level Wei Huang
2021-08-18 16:55 ` [PATCH v3 2/3] KVM: x86: Handle the case of 5-level shadow page table Wei Huang
2021-08-18 17:15   ` Sean Christopherson
2021-08-19 16:36     ` Paolo Bonzini
2021-08-18 18:00   ` Tom Lendacky
2021-08-18 16:55 ` [PATCH v3 3/3] KVM: SVM: Add 5-level page table support for SVM Wei Huang
2021-08-18 17:32   ` Sean Christopherson [this message]
2021-08-19 16:38     ` Paolo Bonzini
2021-08-19 16:43 ` [PATCH v3 0/3] SVM 5-level page table support Paolo Bonzini
2021-08-23  9:20   ` Maxim Levitsky
2021-08-23 15:15     ` Wei Huang
2021-08-23 16:10       ` Sean Christopherson
2021-08-23 18:10         ` Maxim Levitsky
2021-08-23 18:06       ` Maxim Levitsky

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