LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
From: Mike Rapoport <rppt@kernel.org>
To: Vineet Gupta <vgupta@kernel.org>
Cc: linux-snps-arc@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org, Anshuman Khandual <anshuman.khandual@arm.com>
Subject: Re: [PATCH v2 16/19] ARC: mm: support 3 levels of page tables
Date: Tue, 17 Aug 2021 08:03:09 +0300 [thread overview]
Message-ID: <YRtDDZ2PgfGo/eCT@kernel.org> (raw)
In-Reply-To: <3878c8da-cba0-d4f5-90a7-f4024054872d@kernel.org>
On Mon, Aug 16, 2021 at 12:53:46PM -0700, Vineet Gupta wrote:
> On 8/15/21 2:27 AM, Mike Rapoport wrote:
> > On Thu, Aug 12, 2021 at 04:37:50PM -0700, Vineet Gupta wrote:
> > > ARCv2 MMU is software walked and Linux implements 2 levels of paging: pgd/pte.
> > > Forthcoming hw will have multiple levels, so this change preps mm code
> > > for same. It is also fun to try multi levels even on soft-walked code to
> > > ensure generic mm code is robust to handle.
> > >
> > > overview
> > > ________
> > >
> > > 2 levels {pgd, pte} : pmd is folded but pmd_* macros are valid and operate on pgd
> > > 3 levels {pgd, pmd, pte}:
> > > - pud is folded and pud_* macros point to pgd
> > > - pmd_* macros operate on actual pmd
> > >
> > > code changes
> > > ____________
> > >
> > > 1. #include <asm-generic/pgtable-nopud.h>
> > >
> > > 2. Define CONFIG_PGTABLE_LEVELS 3
> > >
> > > 3a. Define PMD_SHIFT, PMD_SIZE, PMD_MASK, pmd_t
> > > 3b. Define pmd_val() which actually deals with pmd
> > > (pmd_offset(), pmd_index() are provided by generic code)
> > > 3c. pmd_alloc_one()/pmd_free() also provided by generic code
> > > (pmd_populate/pmd_free already exist)
> > >
> > > 4. Define pud_none(), pud_bad() macros based on generic pud_val() which
> > > internally pertains to pgd now.
> > > 4b. define pud_populate() to just setup pgd
> > >
> > > Signed-off-by: Vineet Gupta <vgupta@kernel.org>
> > > ---
> > ...
> >
> > > diff --git a/arch/arc/include/asm/pgtable-levels.h b/arch/arc/include/asm/pgtable-levels.h
> > > index 8ece75335bb5..1c2f022d4ad0 100644
> > > --- a/arch/arc/include/asm/pgtable-levels.h
> > > +++ b/arch/arc/include/asm/pgtable-levels.h
> > > @@ -10,6 +10,8 @@
> > > #ifndef _ASM_ARC_PGTABLE_LEVELS_H
> > > #define _ASM_ARC_PGTABLE_LEVELS_H
> > > +#if CONFIG_PGTABLE_LEVELS == 2
> > > +
> > > /*
> > > * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
> > > *
> > > @@ -37,16 +39,38 @@
> > > #define PGDIR_SHIFT 21
> > > #endif
> > > -#define PGDIR_SIZE BIT(PGDIR_SHIFT) /* vaddr span, not PDG sz */
> > > -#define PGDIR_MASK (~(PGDIR_SIZE - 1))
> > > +#else
> > Adding /* CONFIG_PGTABLE_LEVELS == 2 */ would make the whole thing a bit
> > more readable, I think.
>
> You meant
>
> +#else /* CONFIG_PGTABLE_LEVELS != 2
I don't think we are consistent about it in the kernel, there are places
that just copy the condition in #if and some change it to match the #else.
I don't have a preference, up to you.
> >
> > > +
> > > +/*
> > > + * A default 3 level paging testing setup in software walked MMU
> > > + * MMUv4 (8K page): <4> : <7> : <8> : <13>
> > > + */
> > > +#define PGDIR_SHIFT 28
> > > +#if CONFIG_PGTABLE_LEVELS > 2
> > > +#define PMD_SHIFT 21
> > > +#endif
> > > +
> > > +#endif
> > and here as well.
>
> I added following to indicate conditional coding for levels related code
>
> +#endif /* CONFIG_PGTABLE_LEVELS */
>
>
> > > +#define PGDIR_SIZE BIT(PGDIR_SHIFT)
> > > +#define PGDIR_MASK (~(PGDIR_SIZE - 1))
> > > #define PTRS_PER_PGD BIT(32 - PGDIR_SHIFT)
> > > -#define PTRS_PER_PTE BIT(PGDIR_SHIFT - PAGE_SHIFT)
> > > +#if CONFIG_PGTABLE_LEVELS > 2
> > > +#define PMD_SIZE BIT(PMD_SHIFT)
> > > +#define PMD_MASK (~(PMD_SIZE - 1))
> > > +#define PTRS_PER_PMD BIT(PGDIR_SHIFT - PMD_SHIFT)
> > > +#endif
> > > +
> > > +#define PTRS_PER_PTE BIT(PMD_SHIFT - PAGE_SHIFT)
>
--
Sincerely yours,
Mike.
next prev parent reply other threads:[~2021-08-17 5:03 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-12 23:37 [PATCH v2 00/19] ARC mm updates: support 3/4 levels and asm-generic/pgalloc Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 01/19] ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only Vineet Gupta
2021-08-15 9:27 ` Mike Rapoport
2021-08-16 19:45 ` Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 02/19] ARC: mm: remove tlb paranoid code Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 03/19] ARC: mm: move mmu/cache externs out to setup.h Vineet Gupta
2021-08-15 9:27 ` Mike Rapoport
2021-08-16 19:47 ` Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 04/19] ARC: mm: Fixes to allow STRICT_MM_TYPECHECKS Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 05/19] ARC: mm: Enable STRICT_MM_TYPECHECKS Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 06/19] ARC: ioremap: use more commonly used PAGE_KERNEL based uncached flag Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 07/19] ARC: mm: pmd_populate* to use the canonical set_pmd (and drop pmd_set) Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 08/19] ARC: mm: switch pgtable_t back to struct page * Vineet Gupta
2021-08-13 10:45 ` kernel test robot
2021-08-13 14:25 ` Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 09/19] ARC: mm: switch to asm-generic/pgalloc.h Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 10/19] ARC: mm: non-functional code cleanup ahead of 3 levels Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 11/19] ARC: mm: move MMU specific bits out of ASID allocator Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 12/19] ARC: mm: move MMU specific bits out of entry code Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 13/19] ARC: mm: disintegrate mmu.h (arcv2 bits out) Vineet Gupta
2021-08-13 4:01 ` kernel test robot
2021-08-13 14:48 ` Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 14/19] ARC: mm: disintegrate pgtable.h into levels and flags Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 15/19] ARC: mm: hack to allow 2 level build with 4 level code Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 16/19] ARC: mm: support 3 levels of page tables Vineet Gupta
2021-08-15 9:27 ` Mike Rapoport
2021-08-16 19:53 ` Vineet Gupta
2021-08-17 5:03 ` Mike Rapoport [this message]
2021-08-12 23:37 ` [PATCH v2 17/19] ARC: mm: support 4 " Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 18/19] ARC: mm: vmalloc sync from kernel to user table to update PMD Vineet Gupta
2021-08-12 23:37 ` [PATCH v2 19/19] ARC: mm: introduce _PAGE_TABLE to explicitly link pgd,pud,pmd entries Vineet Gupta
2021-08-15 9:26 ` [PATCH v2 00/19] ARC mm updates: support 3/4 levels and asm-generic/pgalloc Mike Rapoport
2021-08-16 19:58 ` Vineet Gupta
2021-08-17 5:04 ` Mike Rapoport
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YRtDDZ2PgfGo/eCT@kernel.org \
--to=rppt@kernel.org \
--cc=anshuman.khandual@arm.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=linux-snps-arc@lists.infradead.org \
--cc=vgupta@kernel.org \
--subject='Re: [PATCH v2 16/19] ARC: mm: support 3 levels of page tables' \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).