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* [PATCH 00/19] Add driver for dvfsrc, support for interconnect
@ 2021-08-12  8:58 Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 01/19] dt-bindings: soc: Add dvfsrc driver bindings Dawei Chien
                   ` (18 more replies)
  0 siblings, 19 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien

This series is based on v5.14-rc1.

The patchsets add support for MediaTek hardware module named DVFSRC
(dynamic voltage and frequency scaling resource collector). The DVFSRC is
a HW module which is used to collect all the requests from both software
and hardware and turn into the decision of minimum operating voltage and
minimum DRAM frequency to fulfill those requests.

So, This series is to implement the dvfsrc driver to collect all the
requests of operating voltage or DRAM bandwidth from other device drivers
likes GPU/Camera through 3 frameworks basically:

1. interconnect framework: to aggregate the bandwidth
   requirements from different clients

[1] https://patchwork.kernel.org/cover/10766329/

There has a hw module "DRAM scheduler", which used to control the
throughput.
The DVFSRC will collect forecast data of dram bandwidth from
SW consumers(camera/gpu...), and according the forecast to change the DRAM
frequency

2. Regualtor framework: to handle the operating voltage requirement from
   user or cosumer which not belong any power domain

Changes in V11:
* rebase all patches on v5.14-rc1.
* support platform mt8195.
* add initial bw in mediatek interconnect driver.
* add one more pcie client in mediatek interconnect driver.
* add compatible for MT8195 dvfsrc.

Changes in V10:
* rebase all patches on v5.13-rc1
* add acked TAG for interconnect provider driver (Georgi)
* update comment message for typos. (Georgi)
* update cover leter for typos.

Changes in V9:
* modify the configuration of dvfsrc.yaml. (Rob)

Changes in V8:
* Fixed the dt_binding_check error of dvfsrc.yaml. (Rob)
* Remove Kconfig dependency of DVFSRC

Changes in V7:
* Fixed the dt_binding_check error of dvfsrc.yaml. (Rob)
* Fixed the checkpatch complains of "Signed-off-by:
email name mismatch". (Georgi)
* Fixed coding style of interconnect driver. (Georgi)
* Update comment of the years to 2021. (Georgi)

Changes in V6:
* Remove the performace state support, because the request from consumer
can be replaced by using interconnect and regulator framework.
* Update the DT patches and convert them to DT schema. (Georgi)
* Modify the comment format and coding style. (Mark)

Changes in V5:
* Support more platform mt6873/mt8192
* Drop the compatible and interconnect provider node and make the parent
node an interconnect provider. (Rob/Georgi)
* Make modification of interconnect driver from coding suggestion. (Georgi)
* Move interconnect diagram into the commit text of patch. (Georgi)
* Register the interconnect provider as a platform sub-device. (Georgi)

Changes in V4:
* Add acked TAG on dt-bindings patches. (Rob)
* Declaration of emi_icc_aggregate since the prototype of aggregate
function has changed meanwhile. (Georgi)
* Used emi_icc_remove instead of icc_provider_del on probe. (Georgi)
* Add dvfsrc regulator driver into series.
* Bug fixed of mt8183_get_current_level.
* Add mutex protection for pstate operation on dvfsrc_set_performance.

Changes in V3:
* Remove RFC from the subject prefix of the series
* Combine dt-binding patch and move interconnect dt-binding document into
dvfsrc. (Rob)
* Remove unused header, add unit descirption to the bandwidth, rename
compatible name on interconnect driver. (Georgi)
* Fixed some coding style: check flow, naming, used readx_poll_timeout
on dvfsrc driver. (Ryan)
* Rename interconnect driver mt8183.c to mtk-emi.c
* Rename interconnect header mtk,mt8183.h to mtk,emi.h
* mtk-scpsys.c: Add opp table check first to avoid OF runtime parse failed

Changes in RFC V2:
* Remove the DT property dram_type. (Rob)
* Used generic dts property 'opp-level' to get the performace
state. (Stephen)
* Remove unnecessary dependency config on Kconfig. (Stephen)
* Remove unused header file, fixed some coding style issue, typo,
error handling on dvfsrc driver. (Nicolas/Stephen)
* Remove irq handler on dvfsrc driver. (Stephen)
* Remove init table on dvfsrc driver, combine hw init on trustzone.
* Add interconnect support of mt8183 to aggregate the emi bandwidth.
(Georgi)

v10: https://patchwork.kernel.org/project/linux-mediatek/list/?series=494095
V9: https://patchwork.kernel.org/project/linux-mediatek/list/?series=440389
V8: https://patchwork.kernel.org/project/linux-mediatek/list/?series=421713
V7: https://patchwork.kernel.org/project/linux-mediatek/list/?series=411057
V6: https://patchwork.kernel.org/project/linux-mediatek/list/?series=406077
V5: https://patchwork.kernel.org/project/linux-mediatek/list/?series=348065
V4: https://lore.kernel.org/patchwork/cover/1209284/
V3: https://patchwork.kernel.org/cover/11118867/
RFC V2: https://lore.kernel.org/patchwork/patch/1068113/
RFC V1: https://lore.kernel.org/patchwork/cover/1028535/

Dawei Chien (8):
  dt-bindings: mediatek: add compatible for MT8195 dvfsrc
  soc: mediatek: add support for mt8195
  arm64: dts: mt8195: add dvfsrc related nodes
  dt-bindings: interconnect: add MT8195 interconnect dt-bindings
  interconnect: mediatek: add support for mt8195
  interconnect: mediatek: add initial bandwidth
  regulator: mediatek: add support for mt8195
  arm64: dts: mt8195: add dvfsrc related nodes

Henry Chen (11):
  dt-bindings: soc: Add dvfsrc driver bindings
  soc: mediatek: add header for mediatek SIP interface
  soc: mediatek: add driver for dvfsrc support
  soc: mediatek: add support for mt6873
  arm64: dts: mt8183: add dvfsrc related nodes
  arm64: dts: mt8192: add dvfsrc related nodes
  dt-bindings: interconnect: add MT6873 interconnect dt-bindings
  interconnect: mediatek: Add interconnect provider driver
  arm64: dts: mt8183: add dvfsrc related nodes
  arm64: dts: mt8192: add dvfsrc related nodes
  arm64: dts: mt8192: add dvfsrc regulator nodes

 .../devicetree/bindings/soc/mediatek/dvfsrc.yaml   |  68 +++
 arch/arm64/boot/dts/mediatek/mt8183.dtsi           |   7 +
 arch/arm64/boot/dts/mediatek/mt8192.dtsi           |  14 +
 arch/arm64/boot/dts/mediatek/mt8195.dtsi           |   7 +
 drivers/interconnect/Kconfig                       |   1 +
 drivers/interconnect/Makefile                      |   1 +
 drivers/interconnect/mediatek/Kconfig              |  13 +
 drivers/interconnect/mediatek/Makefile             |   3 +
 drivers/interconnect/mediatek/mtk-emi.c            | 385 +++++++++++++++
 drivers/regulator/mtk-dvfsrc-regulator.c           |  23 +
 drivers/soc/mediatek/Kconfig                       |  11 +
 drivers/soc/mediatek/Makefile                      |   1 +
 drivers/soc/mediatek/mtk-dvfsrc.c                  | 538 +++++++++++++++++++++
 include/dt-bindings/interconnect/mtk,mt6873-emi.h  |  41 ++
 include/dt-bindings/interconnect/mtk,mt8183-emi.h  |  21 +
 include/dt-bindings/interconnect/mtk,mt8195-emi.h  |  42 ++
 include/linux/soc/mediatek/mtk_dvfsrc.h            |  35 ++
 include/linux/soc/mediatek/mtk_sip_svc.h           |   4 +
 18 files changed, 1215 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
 create mode 100644 drivers/interconnect/mediatek/Kconfig
 create mode 100644 drivers/interconnect/mediatek/Makefile
 create mode 100644 drivers/interconnect/mediatek/mtk-emi.c
 create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
 create mode 100644 include/dt-bindings/interconnect/mtk,mt6873-emi.h
 create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h
 create mode 100644 include/dt-bindings/interconnect/mtk,mt8195-emi.h
 create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h

-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 01/19] dt-bindings: soc: Add dvfsrc driver bindings
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 02/19] dt-bindings: mediatek: add compatible for MT8195 dvfsrc Dawei Chien
                   ` (17 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

Document the binding for enabling dvfsrc on MediaTek SoC.

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/soc/mediatek/dvfsrc.yaml   | 67 ++++++++++++++++++++++
 include/dt-bindings/interconnect/mtk,mt8183-emi.h  | 21 +++++++
 2 files changed, 88 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
 create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h

diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
new file mode 100644
index 000000000000..f2b67b99921b
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/mediatek/dvfsrc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek dynamic voltage and frequency scaling resource collector (DVFSRC)
+
+description: |
+  The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
+  HW module which is used to collect all the requests from both software and
+  hardware and turn into the decision of minimum operating voltage and minimum
+  DRAM frequency to fulfill those requests.
+
+maintainers:
+  - henryc.chen <henryc.chen@mediatek.com>
+
+properties:
+  reg:
+    maxItems: 1
+    description: DVFSRC common register address and length.
+
+  compatible:
+    enum:
+      - mediatek,mt6873-dvfsrc
+      - mediatek,mt8183-dvfsrc
+      - mediatek,mt8192-dvfsrc
+
+  '#interconnect-cells':
+    const: 1
+
+  dvfsrc-vcore:
+    type: object
+    description:
+      The DVFSRC regulator is modelled as a subdevice of the DVFSRC.
+      Because DVFSRC can request power directly via register read/write, likes
+      vcore which is a core power of mt8183. As such, the DVFSRC regulator
+      requires that DVFSRC nodes be present.
+    $ref: /schemas/regulator/regulator.yaml#
+
+required:
+  - compatible
+  - reg
+  - "#interconnect-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interconnect/mtk,mt8183-emi.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        dvfsrc@10012000 {
+            compatible = "mediatek,mt8183-dvfsrc";
+            reg = <0 0x10012000 0 0x1000>;
+            #interconnect-cells = <1>;
+            dvfsrc_vcore: dvfsrc-vcore {
+                    regulator-name = "dvfsrc-vcore";
+                    regulator-min-microvolt = <725000>;
+                    regulator-max-microvolt = <800000>;
+                    regulator-always-on;
+            };
+        };
+    };
diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h b/include/dt-bindings/interconnect/mtk,mt8183-emi.h
new file mode 100644
index 000000000000..dfd143f87885
--- /dev/null
+++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H
+#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H
+
+#define MT8183_SLAVE_DDR_EMI			0
+#define MT8183_MASTER_MCUSYS			1
+#define MT8183_MASTER_GPU			2
+#define MT8183_MASTER_MMSYS			3
+#define MT8183_MASTER_MM_VPU			4
+#define MT8183_MASTER_MM_DISP			5
+#define MT8183_MASTER_MM_VDEC			6
+#define MT8183_MASTER_MM_VENC			7
+#define MT8183_MASTER_MM_CAM			8
+#define MT8183_MASTER_MM_IMG			9
+#define MT8183_MASTER_MM_MDP			10
+
+#endif
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 02/19] dt-bindings: mediatek: add compatible for MT8195 dvfsrc
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 01/19] dt-bindings: soc: Add dvfsrc driver bindings Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-17 21:23   ` Rob Herring
  2021-08-12  8:58 ` [V11,PATCH 03/19] soc: mediatek: add header for mediatek SIP interface Dawei Chien
                   ` (16 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien

This adds dt-binding documentation of dvfsrc for Mediatek MT8195
SoCs Platform.

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
index f2b67b99921b..ec3feaf1ef73 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
@@ -25,6 +25,7 @@ properties:
       - mediatek,mt6873-dvfsrc
       - mediatek,mt8183-dvfsrc
       - mediatek,mt8192-dvfsrc
+      - mediatek,mt8195-dvfsrc
 
   '#interconnect-cells':
     const: 1
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 03/19] soc: mediatek: add header for mediatek SIP interface
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 01/19] dt-bindings: soc: Add dvfsrc driver bindings Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 02/19] dt-bindings: mediatek: add compatible for MT8195 dvfsrc Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2022-02-03 15:14   ` [V11, PATCH " AngeloGioacchino Del Regno
  2021-08-12  8:58 ` [V11,PATCH 04/19] soc: mediatek: add driver for dvfsrc support Dawei Chien
                   ` (15 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

Add a header to collect SIPs and add one SIP call to initialize power
management hardware for the SIP interface defined to access the SPM
handling vcore voltage and ddr rate changes on mt8183 (and most likely
later socs).

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Arvin Wang <arvin.wang@mediatek.com>
---
 include/linux/soc/mediatek/mtk_sip_svc.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h
index 082398e0cfb1..079bbcb361ba 100644
--- a/include/linux/soc/mediatek/mtk_sip_svc.h
+++ b/include/linux/soc/mediatek/mtk_sip_svc.h
@@ -22,4 +22,8 @@
 	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \
 			   ARM_SMCCC_OWNER_SIP, fn_id)
 
+/* VCOREFS */
+#define MTK_SIP_VCOREFS_CONTROL \
+	MTK_SIP_SMC_CMD(0x506)
+
 #endif
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 04/19] soc: mediatek: add driver for dvfsrc support
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (2 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 03/19] soc: mediatek: add header for mediatek SIP interface Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2022-02-03 15:04   ` AngeloGioacchino Del Regno
  2021-08-12  8:58 ` [V11,PATCH 05/19] soc: mediatek: add support for mt6873 Dawei Chien
                   ` (14 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

Add dvfsrc driver for MT6873/MT8183/MT8192

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 drivers/soc/mediatek/Kconfig            |  11 +
 drivers/soc/mediatek/Makefile           |   1 +
 drivers/soc/mediatek/mtk-dvfsrc.c       | 421 ++++++++++++++++++++++++++++++++
 include/linux/soc/mediatek/mtk_dvfsrc.h |  35 +++
 4 files changed, 468 insertions(+)
 create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
 create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h

diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc08569e..2dcf02384639 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -26,6 +26,17 @@ config MTK_DEVAPC
 	  The violation information is logged for further analysis or
 	  countermeasures.
 
+config MTK_DVFSRC
+	tristate "MediaTek DVFSRC Support"
+	depends on ARCH_MEDIATEK
+	help
+	  Say yes here to add support for the MediaTek DVFSRC (dynamic voltage
+	  and frequency scaling resource collector) found
+	  on different MediaTek SoCs. The DVFSRC is a proprietary
+	  hardware which is used to collect all the requests from
+	  system and turn into the decision of minimum Vcore voltage
+	  and minimum DRAM frequency to fulfill those requests.
+
 config MTK_INFRACFG
 	bool "MediaTek INFRACFG Support"
 	select REGMAP
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 90270f8114ed..365d14fd7d49 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
 obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o
+obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
 obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
 obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c
new file mode 100644
index 000000000000..6ef167cf55bd
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/notifier.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk_dvfsrc.h>
+#include <linux/soc/mediatek/mtk_sip_svc.h>
+
+#define DVFSRC_IDLE     0x00
+#define DVFSRC_GET_TARGET_LEVEL(x)  (((x) >> 0) & 0x0000ffff)
+#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x0000ffff)
+#define kbps_to_mbps(x) ((x) / 1000)
+
+#define POLL_TIMEOUT        1000
+#define STARTUP_TIME        1
+
+#define MTK_SIP_DVFSRC_INIT		0x00
+
+#define DVFSRC_OPP_DESC(_opp_table)	\
+{	\
+	.opps = _opp_table,	\
+	.num_opp = ARRAY_SIZE(_opp_table),	\
+}
+
+struct dvfsrc_opp {
+	u32 vcore_opp;
+	u32 dram_opp;
+};
+
+struct dvfsrc_opp_desc {
+	const struct dvfsrc_opp *opps;
+	u32 num_opp;
+};
+
+struct mtk_dvfsrc;
+struct dvfsrc_soc_data {
+	const int *regs;
+	const struct dvfsrc_opp_desc *opps_desc;
+	int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
+	int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
+	u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc);
+	u32 (*get_vcp_level)(struct mtk_dvfsrc *dvfsrc);
+	void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+	void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+	void (*set_dram_hrtbw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
+	void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+	void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+	void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+	int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+	int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
+};
+
+struct mtk_dvfsrc {
+	struct device *dev;
+	struct platform_device *icc;
+	struct platform_device *regulator;
+	const struct dvfsrc_soc_data *dvd;
+	int dram_type;
+	const struct dvfsrc_opp_desc *curr_opps;
+	void __iomem *regs;
+	spinlock_t req_lock;
+	struct mutex pstate_lock;
+	struct notifier_block scpsys_notifier;
+};
+
+static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
+{
+	return readl(dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
+{
+	writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
+}
+
+#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \
+	dvfsrc_write(dvfs, offset, \
+		(dvfsrc_read(dvfs, offset) & ~(mask << shift)) | (val << shift))
+
+enum dvfsrc_regs {
+	DVFSRC_SW_REQ,
+	DVFSRC_SW_REQ2,
+	DVFSRC_LEVEL,
+	DVFSRC_TARGET_LEVEL,
+	DVFSRC_SW_BW,
+	DVFSRC_SW_PEAK_BW,
+	DVFSRC_SW_HRT_BW,
+	DVFSRC_VCORE_REQUEST,
+};
+
+static const int mt8183_regs[] = {
+	[DVFSRC_SW_REQ] =	0x4,
+	[DVFSRC_SW_REQ2] =	0x8,
+	[DVFSRC_LEVEL] =	0xDC,
+	[DVFSRC_SW_BW] =	0x160,
+};
+
+static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc)
+{
+	int level;
+
+	level = dvfsrc->dvd->get_current_level(dvfsrc);
+	return &dvfsrc->curr_opps->opps[level];
+}
+
+static int dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc)
+{
+	if (!dvfsrc->dvd->get_target_level)
+		return true;
+
+	return dvfsrc->dvd->get_target_level(dvfsrc);
+}
+
+static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+	const struct dvfsrc_opp *curr;
+
+	return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr,
+					 curr->vcore_opp >= level, STARTUP_TIME,
+					 POLL_TIMEOUT);
+}
+
+static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+	const struct dvfsrc_opp *target, *curr;
+	int ret;
+
+	target = &dvfsrc->curr_opps->opps[level];
+	ret = readx_poll_timeout(get_current_opp, dvfsrc, curr,
+				 curr->dram_opp >= target->dram_opp &&
+				 curr->vcore_opp >= target->vcore_opp,
+				 STARTUP_TIME, POLL_TIMEOUT);
+	if (ret < 0) {
+		dev_warn(dvfsrc->dev,
+			 "timeout, target: %u, dram: %d, vcore: %d\n", level,
+			 curr->dram_opp, curr->vcore_opp);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mt8183_get_target_level(struct mtk_dvfsrc *dvfsrc)
+{
+	return DVFSRC_GET_TARGET_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL));
+}
+
+static int mt8183_get_current_level(struct mtk_dvfsrc *dvfsrc)
+{
+	int level;
+
+	/* HW level 0 is begin from 0x10000 */
+	level = DVFSRC_GET_CURRENT_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL));
+	/* Array index start from 0 */
+	return ffs(level) - 1;
+}
+
+static u32 mt8183_get_vcore_level(struct mtk_dvfsrc *dvfsrc)
+{
+	return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ2) >> 2) & 0x3;
+}
+
+static void mt8183_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+	dvfsrc_write(dvfsrc, DVFSRC_SW_BW, div_u64(kbps_to_mbps(bw), 100));
+}
+
+static void mt8183_set_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+	int vcore_opp, dram_opp;
+	const struct dvfsrc_opp *opp;
+
+	/* translate pstate to dvfsrc level, and set it to DVFSRC HW */
+	opp = &dvfsrc->curr_opps->opps[level];
+	vcore_opp = opp->vcore_opp;
+	dram_opp = opp->dram_opp;
+
+	dev_dbg(dvfsrc->dev, "vcore_opp: %d, dram_opp: %d\n",
+		vcore_opp, dram_opp);
+	dvfsrc_write(dvfsrc, DVFSRC_SW_REQ, dram_opp | vcore_opp << 2);
+}
+
+static void mt8183_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+	dvfsrc_write(dvfsrc, DVFSRC_SW_REQ2, level << 2);
+}
+
+void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data)
+{
+	int ret, state;
+	struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev);
+
+	dev_dbg(dvfsrc->dev, "cmd: %d, data: %llu\n", cmd, data);
+
+	switch (cmd) {
+	case MTK_DVFSRC_CMD_BW_REQUEST:
+		dvfsrc->dvd->set_dram_bw(dvfsrc, data);
+		return;
+	case MTK_DVFSRC_CMD_PEAK_BW_REQUEST:
+		if (dvfsrc->dvd->set_dram_peak_bw)
+			dvfsrc->dvd->set_dram_peak_bw(dvfsrc, data);
+		return;
+	case MTK_DVFSRC_CMD_OPP_REQUEST:
+		if (dvfsrc->dvd->set_opp_level)
+			dvfsrc->dvd->set_opp_level(dvfsrc, data);
+		break;
+	case MTK_DVFSRC_CMD_VCORE_REQUEST:
+		dvfsrc->dvd->set_vcore_level(dvfsrc, data);
+		break;
+	case MTK_DVFSRC_CMD_HRTBW_REQUEST:
+		if (dvfsrc->dvd->set_dram_hrtbw)
+			dvfsrc->dvd->set_dram_hrtbw(dvfsrc, data);
+		else
+			return;
+		break;
+	case MTK_DVFSRC_CMD_VSCP_REQUEST:
+		dvfsrc->dvd->set_vscp_level(dvfsrc, data);
+		break;
+	default:
+		dev_err(dvfsrc->dev, "unknown command: %d\n", cmd);
+		return;
+	}
+
+	/* DVFSRC needs to wait at least 2T(~196ns) to handle request
+	 * after receiving command
+	 */
+	udelay(STARTUP_TIME);
+
+	ret = readx_poll_timeout(dvfsrc_is_idle, dvfsrc,
+				 state, state == DVFSRC_IDLE,
+				 STARTUP_TIME, POLL_TIMEOUT);
+
+	if (ret < 0) {
+		dev_warn(dvfsrc->dev,
+			 "%d: idle timeout, data: %llu, last: %d -> %d\n",
+			 cmd, data,
+			 dvfsrc->dvd->get_current_level(dvfsrc),
+			 dvfsrc->dvd->get_target_level(dvfsrc));
+		return;
+	}
+
+	/* The previous change may be requested by previous request.
+	 * So we delay 1us, then start checking opp is reached enough.
+	 */
+	udelay(STARTUP_TIME);
+
+	if (cmd == MTK_DVFSRC_CMD_OPP_REQUEST)
+		ret = dvfsrc->dvd->wait_for_opp_level(dvfsrc, data);
+	else
+		ret = dvfsrc->dvd->wait_for_vcore_level(dvfsrc, data);
+
+	if (ret < 0) {
+		dev_warn(dvfsrc->dev,
+			 "%d: wait timeout, data: %llu, last: %d -> %d\n",
+			 cmd, data,
+			 dvfsrc->dvd->get_current_level(dvfsrc),
+			 dvfsrc->dvd->get_target_level(dvfsrc));
+	}
+
+}
+EXPORT_SYMBOL(mtk_dvfsrc_send_request);
+
+int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data)
+{
+	struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev);
+
+	switch (cmd) {
+	case MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY:
+		*data = dvfsrc->dvd->get_vcore_level(dvfsrc);
+		break;
+	case MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY:
+		*data = dvfsrc->dvd->get_vcp_level(dvfsrc);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(mtk_dvfsrc_query_info);
+
+static int mtk_dvfsrc_probe(struct platform_device *pdev)
+{
+	struct arm_smccc_res ares;
+	struct resource *res;
+	struct mtk_dvfsrc *dvfsrc;
+	int ret;
+
+	dvfsrc = devm_kzalloc(&pdev->dev, sizeof(*dvfsrc), GFP_KERNEL);
+	if (!dvfsrc)
+		return -ENOMEM;
+
+	dvfsrc->dvd = of_device_get_match_data(&pdev->dev);
+	dvfsrc->dev = &pdev->dev;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dvfsrc->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(dvfsrc->regs))
+		return PTR_ERR(dvfsrc->regs);
+
+	spin_lock_init(&dvfsrc->req_lock);
+	mutex_init(&dvfsrc->pstate_lock);
+
+	arm_smccc_smc(MTK_SIP_VCOREFS_CONTROL, MTK_SIP_DVFSRC_INIT, 0, 0, 0,
+		0, 0, 0, &ares);
+
+	if (!ares.a0) {
+		dvfsrc->dram_type = ares.a1;
+		dev_info(dvfsrc->dev, "dram_type: %d\n", dvfsrc->dram_type);
+	} else {
+		dev_err(dvfsrc->dev, "init fails: %lu\n", ares.a0);
+		return ares.a0;
+	}
+
+	dvfsrc->curr_opps = &dvfsrc->dvd->opps_desc[dvfsrc->dram_type];
+	platform_set_drvdata(pdev, dvfsrc);
+
+	dvfsrc->regulator = platform_device_register_data(dvfsrc->dev,
+			"mtk-dvfsrc-regulator", -1, NULL, 0);
+	if (IS_ERR(dvfsrc->regulator)) {
+		dev_err(dvfsrc->dev, "Failed create regulator device\n");
+		ret = PTR_ERR(dvfsrc->regulator);
+		goto err;
+	}
+
+	dvfsrc->icc = platform_device_register_data(dvfsrc->dev,
+			"mediatek-emi-icc", -1, NULL, 0);
+	if (IS_ERR(dvfsrc->icc)) {
+		dev_err(dvfsrc->dev, "Failed create icc device\n");
+		ret = PTR_ERR(dvfsrc->icc);
+		goto unregister_regulator;
+	}
+
+	ret = devm_of_platform_populate(&pdev->dev);
+	if (ret)
+		platform_device_unregister(dvfsrc->icc);
+
+	return 0;
+
+unregister_regulator:
+	platform_device_unregister(dvfsrc->regulator);
+err:
+	return ret;
+}
+
+static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp4[] = {
+	{0, 0}, {0, 1}, {0, 2}, {1, 2},
+};
+
+static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp3[] = {
+	{0, 0}, {0, 1}, {1, 1}, {1, 2},
+};
+
+static const struct dvfsrc_opp_desc dvfsrc_opp_mt8183_desc[] = {
+	DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp4),
+	DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp3),
+	DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp3),
+};
+
+static const struct dvfsrc_soc_data mt8183_data = {
+	.opps_desc = dvfsrc_opp_mt8183_desc,
+	.regs = mt8183_regs,
+	.get_target_level = mt8183_get_target_level,
+	.get_current_level = mt8183_get_current_level,
+	.get_vcore_level = mt8183_get_vcore_level,
+	.set_dram_bw = mt8183_set_dram_bw,
+	.set_opp_level = mt8183_set_opp_level,
+	.set_vcore_level = mt8183_set_vcore_level,
+	.wait_for_opp_level = mt8183_wait_for_opp_level,
+	.wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
+};
+
+static int mtk_dvfsrc_remove(struct platform_device *pdev)
+{
+	struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev);
+
+	platform_device_unregister(dvfsrc->regulator);
+	platform_device_unregister(dvfsrc->icc);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_dvfsrc_of_match[] = {
+	{
+		.compatible = "mediatek,mt8183-dvfsrc",
+		.data = &mt8183_data,
+	}, {
+		/* sentinel */
+	},
+};
+
+static struct platform_driver mtk_dvfsrc_driver = {
+	.probe	= mtk_dvfsrc_probe,
+	.remove	= mtk_dvfsrc_remove,
+	.driver = {
+		.name = "mtk-dvfsrc",
+		.of_match_table = of_match_ptr(mtk_dvfsrc_of_match),
+	},
+};
+
+static int __init mtk_dvfsrc_init(void)
+{
+	return platform_driver_register(&mtk_dvfsrc_driver);
+}
+subsys_initcall(mtk_dvfsrc_init);
+
+static void __exit mtk_dvfsrc_exit(void)
+{
+	platform_driver_unregister(&mtk_dvfsrc_driver);
+}
+module_exit(mtk_dvfsrc_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("MTK DVFSRC driver");
diff --git a/include/linux/soc/mediatek/mtk_dvfsrc.h b/include/linux/soc/mediatek/mtk_dvfsrc.h
new file mode 100644
index 000000000000..823eff9bb19f
--- /dev/null
+++ b/include/linux/soc/mediatek/mtk_dvfsrc.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __SOC_MTK_DVFSRC_H
+#define __SOC_MTK_DVFSRC_H
+
+#define MTK_DVFSRC_CMD_BW_REQUEST		0
+#define MTK_DVFSRC_CMD_OPP_REQUEST		1
+#define MTK_DVFSRC_CMD_VCORE_REQUEST		2
+#define MTK_DVFSRC_CMD_HRTBW_REQUEST		3
+#define MTK_DVFSRC_CMD_VSCP_REQUEST		4
+#define MTK_DVFSRC_CMD_PEAK_BW_REQUEST		5
+
+#define MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY	0
+#define MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY		1
+
+#if IS_ENABLED(CONFIG_MTK_DVFSRC)
+void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data);
+int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data);
+
+#else
+
+static inline void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd,
+					   u64 data)
+{ return -ENODEV; }
+
+static inline int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd,
+					int *data);
+{ return -ENODEV; }
+
+#endif /* CONFIG_MTK_DVFSRC */
+
+#endif
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 05/19] soc: mediatek: add support for mt6873
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (3 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 04/19] soc: mediatek: add driver for dvfsrc support Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2022-02-03 15:13   ` AngeloGioacchino Del Regno
  2021-08-12  8:58 ` [V11,PATCH 06/19] soc: mediatek: add support for mt8195 Dawei Chien
                   ` (13 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

add support for mt6873

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
---
 drivers/soc/mediatek/mtk-dvfsrc.c | 114 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c
index 6ef167cf55bd..1f053367eabe 100644
--- a/drivers/soc/mediatek/mtk-dvfsrc.c
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -102,6 +102,16 @@ static const int mt8183_regs[] = {
 	[DVFSRC_SW_BW] =	0x160,
 };
 
+static const int mt6873_regs[] = {
+	[DVFSRC_SW_REQ] =		0xC,
+	[DVFSRC_LEVEL] =		0xD44,
+	[DVFSRC_SW_PEAK_BW] =		0x278,
+	[DVFSRC_SW_BW] =		0x26C,
+	[DVFSRC_SW_HRT_BW] =		0x290,
+	[DVFSRC_TARGET_LEVEL] =		0xD48,
+	[DVFSRC_VCORE_REQUEST] =	0x6C,
+};
+
 static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc)
 {
 	int level;
@@ -127,6 +137,78 @@ static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level)
 					 POLL_TIMEOUT);
 }
 
+static int mt6873_get_target_level(struct mtk_dvfsrc *dvfsrc)
+{
+	return dvfsrc_read(dvfsrc, DVFSRC_TARGET_LEVEL);
+}
+
+static int mt6873_get_current_level(struct mtk_dvfsrc *dvfsrc)
+{
+	u32 curr_level;
+
+	/* HW level 0 is begin from 0x1, and max opp is 0x1*/
+	curr_level = ffs(dvfsrc_read(dvfsrc, DVFSRC_LEVEL));
+	if (curr_level > dvfsrc->curr_opps->num_opp)
+		curr_level = 0;
+	else
+		curr_level = dvfsrc->curr_opps->num_opp - curr_level;
+
+	return curr_level;
+}
+
+static int mt6873_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+	const struct dvfsrc_opp *target, *curr;
+
+	target = &dvfsrc->curr_opps->opps[level];
+	return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr,
+		curr->dram_opp >= target->dram_opp,
+		STARTUP_TIME, POLL_TIMEOUT);
+}
+
+static u32 mt6873_get_vcore_level(struct mtk_dvfsrc *dvfsrc)
+{
+	return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ) >> 4) & 0x7;
+}
+
+static u32 mt6873_get_vcp_level(struct mtk_dvfsrc *dvfsrc)
+{
+	return (dvfsrc_read(dvfsrc, DVFSRC_VCORE_REQUEST) >> 12) & 0x7;
+}
+
+static void mt6873_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+	bw = div_u64(kbps_to_mbps(bw), 100);
+	bw = min_t(u64, bw, 0xFF);
+	dvfsrc_write(dvfsrc, DVFSRC_SW_BW, bw);
+}
+
+static void mt6873_set_dram_peak_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+	bw = div_u64(kbps_to_mbps(bw), 100);
+	bw = min_t(u64, bw, 0xFF);
+	dvfsrc_write(dvfsrc, DVFSRC_SW_PEAK_BW, bw);
+}
+
+static void mt6873_set_dram_hrtbw(struct mtk_dvfsrc *dvfsrc, u64 bw)
+{
+	bw = div_u64((kbps_to_mbps(bw) + 29), 30);
+	bw = min_t(u64, bw, 0x3FF);
+	dvfsrc_write(dvfsrc, DVFSRC_SW_HRT_BW, bw);
+}
+
+static void mt6873_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+	spin_lock(&dvfsrc->req_lock);
+	dvfsrc_rmw(dvfsrc, DVFSRC_SW_REQ, level, 0x7, 4);
+	spin_unlock(&dvfsrc->req_lock);
+}
+
+static void mt6873_set_vscp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
+{
+	dvfsrc_rmw(dvfsrc, DVFSRC_VCORE_REQUEST, level, 0x7, 12);
+}
+
 static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
 {
 	const struct dvfsrc_opp *target, *curr;
@@ -377,6 +459,35 @@ static const struct dvfsrc_soc_data mt8183_data = {
 	.wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
 };
 
+static const struct dvfsrc_opp dvfsrc_opp_mt6873_lp4[] = {
+	{0, 0}, {1, 0}, {2, 0}, {3, 0},
+	{0, 1}, {1, 1}, {2, 1}, {3, 1},
+	{0, 2}, {1, 2}, {2, 2}, {3, 2},
+	{1, 3}, {2, 3}, {3, 3}, {1, 4},
+	{2, 4}, {3, 4}, {2, 5}, {3, 5},
+	{3, 6},
+};
+
+static const struct dvfsrc_opp_desc dvfsrc_opp_mt6873_desc[] = {
+	DVFSRC_OPP_DESC(dvfsrc_opp_mt6873_lp4),
+};
+
+static const struct dvfsrc_soc_data mt6873_data = {
+	.opps_desc = dvfsrc_opp_mt6873_desc,
+	.regs = mt6873_regs,
+	.get_target_level = mt6873_get_target_level,
+	.get_current_level = mt6873_get_current_level,
+	.get_vcore_level = mt6873_get_vcore_level,
+	.get_vcp_level = mt6873_get_vcp_level,
+	.set_dram_bw = mt6873_set_dram_bw,
+	.set_dram_peak_bw = mt6873_set_dram_peak_bw,
+	.set_dram_hrtbw = mt6873_set_dram_hrtbw,
+	.set_vcore_level = mt6873_set_vcore_level,
+	.set_vscp_level = mt6873_set_vscp_level,
+	.wait_for_opp_level = mt6873_wait_for_opp_level,
+	.wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
+};
+
 static int mtk_dvfsrc_remove(struct platform_device *pdev)
 {
 	struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev);
@@ -391,6 +502,9 @@ static const struct of_device_id mtk_dvfsrc_of_match[] = {
 	{
 		.compatible = "mediatek,mt8183-dvfsrc",
 		.data = &mt8183_data,
+	}, {
+		.compatible = "mediatek,mt6873-dvfsrc",
+		.data = &mt6873_data,
 	}, {
 		/* sentinel */
 	},
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 06/19] soc: mediatek: add support for mt8195
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (4 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 05/19] soc: mediatek: add support for mt6873 Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 07/19] arm64: dts: mt8183: add dvfsrc related nodes Dawei Chien
                   ` (12 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien

add support for mt8195

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 drivers/soc/mediatek/mtk-dvfsrc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c
index 1f053367eabe..692846d8b233 100644
--- a/drivers/soc/mediatek/mtk-dvfsrc.c
+++ b/drivers/soc/mediatek/mtk-dvfsrc.c
@@ -505,6 +505,9 @@ static const struct of_device_id mtk_dvfsrc_of_match[] = {
 	}, {
 		.compatible = "mediatek,mt6873-dvfsrc",
 		.data = &mt6873_data,
+	}, {
+		.compatible = "mediatek,mt8195-dvfsrc",
+		.data = &mt6873_data,
 	}, {
 		/* sentinel */
 	},
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 07/19] arm64: dts: mt8183: add dvfsrc related nodes
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (5 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 06/19] soc: mediatek: add support for mt8195 Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 08/19] arm64: dts: mt8192: " Dawei Chien
                   ` (11 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

Enable dvfsrc on mt8183 platform.

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index f90df6439c08..7ad4cf646579 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -583,6 +583,11 @@
 			#clock-cells = <1>;
 		};
 
+		ddr_emi: dvfsrc@10012000 {
+			compatible = "mediatek,mt8183-dvfsrc";
+			reg = <0 0x10012000 0 0x1000>;
+		};
+
 		pwrap: pwrap@1000d000 {
 			compatible = "mediatek,mt8183-pwrap";
 			reg = <0 0x1000d000 0 0x1000>;
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 08/19] arm64: dts: mt8192: add dvfsrc related nodes
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (6 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 07/19] arm64: dts: mt8183: add dvfsrc related nodes Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 09/19] arm64: dts: mt8195: " Dawei Chien
                   ` (10 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

Enable dvfsrc on mt8192 platform.

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 9757138a8bbd..c70a3bf744fa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -282,6 +282,12 @@
 			#interrupt-cells = <2>;
 		};
 
+		ddr_emi: dvfsrc@10012000 {
+			compatible = "mediatek,mt8192-dvfsrc",
+				     "mediatek,mt6873-dvfsrc";
+			reg = <0 0x10012000 0 0x1000>;
+		};
+
 		systimer: timer@10017000 {
 			compatible = "mediatek,mt8192-timer",
 				     "mediatek,mt6765-timer";
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 09/19] arm64: dts: mt8195: add dvfsrc related nodes
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (7 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 08/19] arm64: dts: mt8192: " Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 10/19] dt-bindings: interconnect: add MT6873 interconnect dt-bindings Dawei Chien
                   ` (9 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien

Enable dvfsrc on mt8195 platform.

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index c146a91c6272..19430f324ee1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -686,6 +686,11 @@
 			#clock-cells = <1>;
 		};
 
+		ddr_emi: dvfsrc@10012000 {
+			compatible = "mediatek,mt8195-dvfsrc";
+			reg = <0 0x10012000 0 0x1000>;
+		};
+
 		systimer: timer@10017000 {
 			compatible = "mediatek,mt8195-timer", "mediatek,mt6765-timer";
 			reg = <0 0x10017000 0 0x1000>;
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 10/19] dt-bindings: interconnect: add MT6873 interconnect dt-bindings
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (8 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 09/19] arm64: dts: mt8195: " Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 11/19] dt-bindings: interconnect: add MT8195 " Dawei Chien
                   ` (8 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

Add interconnect provider dt-bindings for MT6873.

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 include/dt-bindings/interconnect/mtk,mt6873-emi.h | 41 +++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 include/dt-bindings/interconnect/mtk,mt6873-emi.h

diff --git a/include/dt-bindings/interconnect/mtk,mt6873-emi.h b/include/dt-bindings/interconnect/mtk,mt6873-emi.h
new file mode 100644
index 000000000000..0b20011df010
--- /dev/null
+++ b/include/dt-bindings/interconnect/mtk,mt6873-emi.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H
+#define __DT_BINDINGS_INTERCONNECT_MTK_MT6873_EMI_H
+
+#define MT6873_SLAVE_DDR_EMI		0
+#define MT6873_MASTER_MCUSYS		1
+#define MT6873_MASTER_GPUSYS		2
+#define MT6873_MASTER_MMSYS		3
+#define MT6873_MASTER_MM_VPU		4
+#define MT6873_MASTER_MM_DISP		5
+#define MT6873_MASTER_MM_VDEC		6
+#define MT6873_MASTER_MM_VENC		7
+#define MT6873_MASTER_MM_CAM		8
+#define MT6873_MASTER_MM_IMG		9
+#define MT6873_MASTER_MM_MDP		10
+#define MT6873_MASTER_VPUSYS		11
+#define MT6873_MASTER_VPU_0		12
+#define MT6873_MASTER_VPU_1		13
+#define MT6873_MASTER_MDLASYS		14
+#define MT6873_MASTER_MDLA_0		15
+#define MT6873_MASTER_UFS		16
+#define MT6873_MASTER_PCIE		17
+#define MT6873_MASTER_USB		18
+#define MT6873_MASTER_DBGIF		19
+#define MT6873_SLAVE_HRT_DDR_EMI	20
+#define MT6873_MASTER_HRT_MMSYS		21
+#define MT6873_MASTER_HRT_MM_DISP	22
+#define MT6873_MASTER_HRT_MM_VDEC	23
+#define MT6873_MASTER_HRT_MM_VENC	24
+#define MT6873_MASTER_HRT_MM_CAM	25
+#define MT6873_MASTER_HRT_MM_IMG	26
+#define MT6873_MASTER_HRT_MM_MDP	27
+#define MT6873_MASTER_HRT_DBGIF		28
+#define MT6873_MASTER_WIFI		29
+#define MT6873_MASTER_BT		30
+#define MT6873_MASTER_NETSYS		31
+#endif
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 11/19] dt-bindings: interconnect: add MT8195 interconnect dt-bindings
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (9 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 10/19] dt-bindings: interconnect: add MT6873 interconnect dt-bindings Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-17 21:24   ` Rob Herring
  2022-02-03 15:22   ` [V11, PATCH " AngeloGioacchino Del Regno
  2021-08-12  8:58 ` [V11,PATCH 12/19] interconnect: mediatek: Add interconnect provider driver Dawei Chien
                   ` (7 subsequent siblings)
  18 siblings, 2 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien

Add interconnect provider dt-bindings for MT8195

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 include/dt-bindings/interconnect/mtk,mt8195-emi.h | 42 +++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 include/dt-bindings/interconnect/mtk,mt8195-emi.h

diff --git a/include/dt-bindings/interconnect/mtk,mt8195-emi.h b/include/dt-bindings/interconnect/mtk,mt8195-emi.h
new file mode 100644
index 000000000000..c7e8b805f8bd
--- /dev/null
+++ b/include/dt-bindings/interconnect/mtk,mt8195-emi.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8195_EMI_H
+#define __DT_BINDINGS_INTERCONNECT_MTK_MT8195_EMI_H
+
+#define MT8195_SLAVE_DDR_EMI		0
+#define MT8195_MASTER_MCUSYS		1
+#define MT8195_MASTER_GPUSYS		2
+#define MT8195_MASTER_MMSYS		3
+#define MT8195_MASTER_MM_VPU		4
+#define MT8195_MASTER_MM_DISP		5
+#define MT8195_MASTER_MM_VDEC		6
+#define MT8195_MASTER_MM_VENC		7
+#define MT8195_MASTER_MM_CAM		8
+#define MT8195_MASTER_MM_IMG		9
+#define MT8195_MASTER_MM_MDP		10
+#define MT8195_MASTER_VPUSYS		11
+#define MT8195_MASTER_VPU_0		12
+#define MT8195_MASTER_VPU_1		13
+#define MT8195_MASTER_MDLASYS		14
+#define MT8195_MASTER_MDLA_0		15
+#define MT8195_MASTER_UFS		16
+#define MT8195_MASTER_PCIE_0		17
+#define MT8195_MASTER_PCIE_1		18
+#define MT8195_MASTER_USB		19
+#define MT8195_MASTER_DBGIF		20
+#define MT8195_SLAVE_HRT_DDR_EMI	21
+#define MT8195_MASTER_HRT_MMSYS		22
+#define MT8195_MASTER_HRT_MM_DISP	23
+#define MT8195_MASTER_HRT_MM_VDEC	24
+#define MT8195_MASTER_HRT_MM_VENC	25
+#define MT8195_MASTER_HRT_MM_CAM	26
+#define MT8195_MASTER_HRT_MM_IMG	27
+#define MT8195_MASTER_HRT_MM_MDP	28
+#define MT8195_MASTER_HRT_DBGIF		29
+#define MT8195_MASTER_WIFI		30
+#define MT8195_MASTER_BT		31
+#define MT8195_MASTER_NETSYS		32
+#endif
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 12/19] interconnect: mediatek: Add interconnect provider driver
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (10 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 11/19] dt-bindings: interconnect: add MT8195 " Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2022-02-03 15:19   ` [V11, PATCH " AngeloGioacchino Del Regno
  2021-08-12  8:58 ` [V11,PATCH 13/19] interconnect: mediatek: add support for mt8195 Dawei Chien
                   ` (6 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver
using the interconnect framework.

             ICC provider         ICC Nodes
                              ----          ----
             ---------       |CPU |   |--- |VPU |
    -----   |         |-----  ----    |     ----
   |DRAM |--|DRAM     |       ----    |     ----
   |     |--|scheduler|----- |GPU |   |--- |DISP|
   |     |--|(EMI)    |       ----    |     ----
   |     |--|         |       -----   |     ----
    -----   |         |----- |MMSYS|--|--- |VDEC|
             ---------        -----   |     ----
               /|\                    |     ----
                |change DRAM freq     |--- |VENC|
             ----------               |     ----
            |  DVFSR   |              |
            |          |              |     ----
             ----------               |--- |IMG |
                                      |     ----
                                      |     ----
                                      |--- |CAM |
                                            ----
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Reviewed-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 drivers/interconnect/Kconfig            |   1 +
 drivers/interconnect/Makefile           |   1 +
 drivers/interconnect/mediatek/Kconfig   |  13 ++
 drivers/interconnect/mediatek/Makefile  |   3 +
 drivers/interconnect/mediatek/mtk-emi.c | 331 ++++++++++++++++++++++++++++++++
 5 files changed, 349 insertions(+)
 create mode 100644 drivers/interconnect/mediatek/Kconfig
 create mode 100644 drivers/interconnect/mediatek/Makefile
 create mode 100644 drivers/interconnect/mediatek/mtk-emi.c

diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
index d637a89d4695..da91f847aabd 100644
--- a/drivers/interconnect/Kconfig
+++ b/drivers/interconnect/Kconfig
@@ -12,6 +12,7 @@ menuconfig INTERCONNECT
 if INTERCONNECT
 
 source "drivers/interconnect/imx/Kconfig"
+source "drivers/interconnect/mediatek/Kconfig"
 source "drivers/interconnect/qcom/Kconfig"
 source "drivers/interconnect/samsung/Kconfig"
 
diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
index 97d393fd638d..d697500d99f0 100644
--- a/drivers/interconnect/Makefile
+++ b/drivers/interconnect/Makefile
@@ -5,5 +5,6 @@ icc-core-objs				:= core.o bulk.o
 
 obj-$(CONFIG_INTERCONNECT)		+= icc-core.o
 obj-$(CONFIG_INTERCONNECT_IMX)		+= imx/
+obj-$(CONFIG_INTERCONNECT_MTK)		+= mediatek/
 obj-$(CONFIG_INTERCONNECT_QCOM)		+= qcom/
 obj-$(CONFIG_INTERCONNECT_SAMSUNG)	+= samsung/
diff --git a/drivers/interconnect/mediatek/Kconfig b/drivers/interconnect/mediatek/Kconfig
new file mode 100644
index 000000000000..ec98d6a80f55
--- /dev/null
+++ b/drivers/interconnect/mediatek/Kconfig
@@ -0,0 +1,13 @@
+config INTERCONNECT_MTK
+	bool "Mediatek Network-on-Chip interconnect drivers"
+	depends on ARCH_MEDIATEK || COMPILE_TEST
+	help
+	  Support for Mediatek's Network-on-Chip interconnect hardware.
+
+config INTERCONNECT_MTK_EMI
+	tristate "Mediatek EMI interconnect driver"
+	depends on INTERCONNECT_MTK
+	depends on (MTK_DVFSRC && OF) || COMPILE_TEST
+	help
+	  This is a driver for the Mediatek Network-on-Chip on DVFSRC-based
+	  platforms.
diff --git a/drivers/interconnect/mediatek/Makefile b/drivers/interconnect/mediatek/Makefile
new file mode 100644
index 000000000000..353842b2c273
--- /dev/null
+++ b/drivers/interconnect/mediatek/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_INTERCONNECT_MTK_EMI) += mtk-emi.o
\ No newline at end of file
diff --git a/drivers/interconnect/mediatek/mtk-emi.c b/drivers/interconnect/mediatek/mtk-emi.c
new file mode 100644
index 000000000000..8d650be62b90
--- /dev/null
+++ b/drivers/interconnect/mediatek/mtk-emi.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk_dvfsrc.h>
+#include <dt-bindings/interconnect/mtk,mt6873-emi.h>
+#include <dt-bindings/interconnect/mtk,mt8183-emi.h>
+
+enum mtk_icc_name {
+	SLAVE_DDR_EMI,
+	MASTER_MCUSYS,
+	MASTER_GPUSYS,
+	MASTER_MMSYS,
+	MASTER_MM_VPU,
+	MASTER_MM_DISP,
+	MASTER_MM_VDEC,
+	MASTER_MM_VENC,
+	MASTER_MM_CAM,
+	MASTER_MM_IMG,
+	MASTER_MM_MDP,
+	MASTER_VPUSYS,
+	MASTER_VPU_PORT_0,
+	MASTER_VPU_PORT_1,
+	MASTER_MDLASYS,
+	MASTER_MDLA_PORT_0,
+	MASTER_UFS,
+	MASTER_PCIE,
+	MASTER_USB,
+	MASTER_WIFI,
+	MASTER_BT,
+	MASTER_NETSYS,
+	MASTER_DBGIF,
+
+	SLAVE_HRT_DDR_EMI,
+	MASTER_HRT_MMSYS,
+	MASTER_HRT_MM_DISP,
+	MASTER_HRT_MM_VDEC,
+	MASTER_HRT_MM_VENC,
+	MASTER_HRT_MM_CAM,
+	MASTER_HRT_MM_IMG,
+	MASTER_HRT_MM_MDP,
+	MASTER_HRT_DBGIF,
+};
+
+#define MT8183_MAX_LINKS	1
+
+/**
+ * struct mtk_icc_node - Mediatek specific interconnect nodes
+ * @name: the node name used in debugfs
+ * @ep : the type of this endpoint
+ * @id: a unique node identifier
+ * @links: an array of nodes where we can go next while traversing
+ * @num_links: the total number of @links
+ * @sum_avg: current sum aggregate value of all avg bw kBps requests
+ * @max_peak: current max aggregate value of all peak bw kBps requests
+ */
+struct mtk_icc_node {
+	unsigned char *name;
+	int ep;
+	u16 id;
+	u16 links[MT8183_MAX_LINKS];
+	u16 num_links;
+	u64 sum_avg;
+	u64 max_peak;
+};
+
+struct mtk_icc_desc {
+	struct mtk_icc_node **nodes;
+	size_t num_nodes;
+};
+
+#define DEFINE_MNODE(_name, _id, _ep, ...)	\
+		static struct mtk_icc_node _name = {			\
+		.name = #_name,						\
+		.id = _id,						\
+		.ep = _ep,						\
+		.num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })),	\
+		.links = { __VA_ARGS__ },				\
+}
+
+DEFINE_MNODE(ddr_emi, SLAVE_DDR_EMI, 1);
+DEFINE_MNODE(mcusys, MASTER_MCUSYS, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(gpu, MASTER_GPUSYS, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(mmsys, MASTER_MMSYS, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(mm_vpu, MASTER_MM_VPU, 0, MASTER_MMSYS);
+DEFINE_MNODE(mm_disp, MASTER_MM_DISP, 0, MASTER_MMSYS);
+DEFINE_MNODE(mm_vdec, MASTER_MM_VDEC, 0, MASTER_MMSYS);
+DEFINE_MNODE(mm_venc, MASTER_MM_VENC, 0, MASTER_MMSYS);
+DEFINE_MNODE(mm_cam, MASTER_MM_CAM, 0, MASTER_MMSYS);
+DEFINE_MNODE(mm_img, MASTER_MM_IMG, 0, MASTER_MMSYS);
+DEFINE_MNODE(mm_mdp, MASTER_MM_MDP, 0, MASTER_MMSYS);
+DEFINE_MNODE(vpusys, MASTER_VPUSYS, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(vpu_port_0, MASTER_VPU_PORT_0, 0, MASTER_VPUSYS);
+DEFINE_MNODE(vpu_port_1, MASTER_VPU_PORT_1, 0, MASTER_VPUSYS);
+DEFINE_MNODE(mdlasys, MASTER_MDLASYS, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(mdla_port_0, MASTER_MDLA_PORT_0, 0, MASTER_MDLASYS);
+DEFINE_MNODE(ufs, MASTER_UFS, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(pcie, MASTER_PCIE, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(usb, MASTER_USB, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(wifi, MASTER_WIFI, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(bt, MASTER_BT, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(netsys, MASTER_NETSYS, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(dbgif, MASTER_DBGIF, 0, SLAVE_DDR_EMI);
+
+DEFINE_MNODE(hrt_ddr_emi, SLAVE_HRT_DDR_EMI, 2);
+DEFINE_MNODE(hrt_mmsys, MASTER_HRT_MMSYS, 0, SLAVE_HRT_DDR_EMI);
+DEFINE_MNODE(hrt_mm_disp, MASTER_HRT_MM_DISP, 0, MASTER_HRT_MMSYS);
+DEFINE_MNODE(hrt_mm_vdec, MASTER_HRT_MM_VDEC, 0, MASTER_HRT_MMSYS);
+DEFINE_MNODE(hrt_mm_venc, MASTER_HRT_MM_VENC, 0, MASTER_HRT_MMSYS);
+DEFINE_MNODE(hrt_mm_cam, MASTER_HRT_MM_CAM, 0, MASTER_HRT_MMSYS);
+DEFINE_MNODE(hrt_mm_img, MASTER_HRT_MM_IMG, 0, MASTER_HRT_MMSYS);
+DEFINE_MNODE(hrt_mm_mdp, MASTER_HRT_MM_MDP, 0, MASTER_HRT_MMSYS);
+DEFINE_MNODE(hrt_dbgif, MASTER_HRT_DBGIF, 0, SLAVE_HRT_DDR_EMI);
+
+static struct mtk_icc_node *mt8183_icc_nodes[] = {
+	[MT8183_SLAVE_DDR_EMI] = &ddr_emi,
+	[MT8183_MASTER_MCUSYS] = &mcusys,
+	[MT8183_MASTER_GPU] = &gpu,
+	[MT8183_MASTER_MMSYS] = &mmsys,
+	[MT8183_MASTER_MM_VPU] = &mm_vpu,
+	[MT8183_MASTER_MM_DISP] = &mm_disp,
+	[MT8183_MASTER_MM_VDEC] = &mm_vdec,
+	[MT8183_MASTER_MM_VENC] = &mm_venc,
+	[MT8183_MASTER_MM_CAM] = &mm_cam,
+	[MT8183_MASTER_MM_IMG] = &mm_img,
+	[MT8183_MASTER_MM_MDP] = &mm_mdp,
+};
+
+static const struct mtk_icc_desc mt8183_icc = {
+	.nodes = mt8183_icc_nodes,
+	.num_nodes = ARRAY_SIZE(mt8183_icc_nodes),
+};
+
+static struct mtk_icc_node *mt6873_icc_nodes[] = {
+	[MT6873_SLAVE_DDR_EMI] = &ddr_emi,
+	[MT6873_MASTER_MCUSYS] = &mcusys,
+	[MT6873_MASTER_GPUSYS] = &gpu,
+	[MT6873_MASTER_MMSYS] = &mmsys,
+	[MT6873_MASTER_MM_VPU] = &mm_vpu,
+	[MT6873_MASTER_MM_DISP] = &mm_disp,
+	[MT6873_MASTER_MM_VDEC] = &mm_vdec,
+	[MT6873_MASTER_MM_VENC] = &mm_venc,
+	[MT6873_MASTER_MM_CAM] = &mm_cam,
+	[MT6873_MASTER_MM_IMG] = &mm_img,
+	[MT6873_MASTER_MM_MDP] = &mm_mdp,
+	[MT6873_MASTER_VPUSYS] = &vpusys,
+	[MT6873_MASTER_VPU_0] = &vpu_port_0,
+	[MT6873_MASTER_VPU_1] = &vpu_port_1,
+	[MT6873_MASTER_MDLASYS] = &mdlasys,
+	[MT6873_MASTER_MDLA_0] = &mdla_port_0,
+	[MT6873_MASTER_UFS] = &ufs,
+	[MT6873_MASTER_PCIE] = &pcie,
+	[MT6873_MASTER_USB] = &usb,
+	[MT6873_MASTER_WIFI] = &wifi,
+	[MT6873_MASTER_BT] = &bt,
+	[MT6873_MASTER_NETSYS] = &netsys,
+	[MT6873_MASTER_DBGIF] = &dbgif,
+
+	[MT6873_SLAVE_HRT_DDR_EMI] = &hrt_ddr_emi,
+	[MT6873_MASTER_HRT_MMSYS] = &hrt_mmsys,
+	[MT6873_MASTER_HRT_MM_DISP] = &hrt_mm_disp,
+	[MT6873_MASTER_HRT_MM_VDEC] = &hrt_mm_vdec,
+	[MT6873_MASTER_HRT_MM_VENC] = &hrt_mm_venc,
+	[MT6873_MASTER_HRT_MM_CAM] = &hrt_mm_cam,
+	[MT6873_MASTER_HRT_MM_IMG] = &hrt_mm_img,
+	[MT6873_MASTER_HRT_MM_MDP] = &hrt_mm_mdp,
+	[MT6873_MASTER_HRT_DBGIF] = &hrt_dbgif,
+};
+
+static struct mtk_icc_desc mt6873_icc = {
+	.nodes = mt6873_icc_nodes,
+	.num_nodes = ARRAY_SIZE(mt6873_icc_nodes),
+};
+
+static const struct of_device_id emi_icc_of_match[] = {
+	{ .compatible = "mediatek,mt8183-dvfsrc", .data = &mt8183_icc },
+	{ .compatible = "mediatek,mt8192-dvfsrc", .data = &mt6873_icc },
+	{ .compatible = "mediatek,mt6873-dvfsrc", .data = &mt6873_icc },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, emi_icc_of_match);
+
+static int emi_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
+			     u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
+{
+	struct mtk_icc_node *in;
+
+	in = node->data;
+
+	*agg_avg += avg_bw;
+	*agg_peak = max_t(u32, *agg_peak, peak_bw);
+
+	in->sum_avg = *agg_avg;
+	in->max_peak = *agg_peak;
+
+	return 0;
+}
+
+static int emi_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+	int ret = 0;
+	struct mtk_icc_node *node;
+
+	node = dst->data;
+
+	if (node->ep == 1) {
+		mtk_dvfsrc_send_request(src->provider->dev,
+					MTK_DVFSRC_CMD_PEAK_BW_REQUEST,
+					node->max_peak);
+		mtk_dvfsrc_send_request(src->provider->dev,
+					MTK_DVFSRC_CMD_BW_REQUEST,
+					node->sum_avg);
+	} else if (node->ep == 2) {
+		mtk_dvfsrc_send_request(src->provider->dev,
+					MTK_DVFSRC_CMD_HRTBW_REQUEST,
+					node->sum_avg);
+	}
+
+	return ret;
+}
+
+static int emi_icc_remove(struct platform_device *pdev);
+static int emi_icc_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	const struct mtk_icc_desc *desc;
+	struct device *dev = &pdev->dev;
+	struct icc_node *node;
+	struct icc_onecell_data *data;
+	struct icc_provider *provider;
+	struct mtk_icc_node **mnodes;
+	size_t num_nodes, i, j;
+	int ret;
+
+	match = of_match_node(emi_icc_of_match, dev->parent->of_node);
+
+	if (!match) {
+		dev_err(dev, "invalid compatible string\n");
+		return -ENODEV;
+	}
+
+	desc = match->data;
+	mnodes = desc->nodes;
+	num_nodes = desc->num_nodes;
+
+	provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
+	if (!provider)
+		return -ENOMEM;
+
+	data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
+			    GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	provider->dev = pdev->dev.parent;
+	provider->set = emi_icc_set;
+	provider->aggregate = emi_icc_aggregate;
+	provider->xlate = of_icc_xlate_onecell;
+	INIT_LIST_HEAD(&provider->nodes);
+	provider->data = data;
+
+	ret = icc_provider_add(provider);
+	if (ret) {
+		dev_err(&pdev->dev, "error adding interconnect provider\n");
+		return ret;
+	}
+
+	for (i = 0; i < num_nodes; i++) {
+		node = icc_node_create(mnodes[i]->id);
+		if (IS_ERR(node)) {
+			ret = PTR_ERR(node);
+			goto err;
+		}
+
+		node->name = mnodes[i]->name;
+		node->data = mnodes[i];
+		icc_node_add(node, provider);
+
+		for (j = 0; j < mnodes[i]->num_links; j++)
+			icc_link_create(node, mnodes[i]->links[j]);
+
+		data->nodes[i] = node;
+	}
+	data->num_nodes = num_nodes;
+
+	platform_set_drvdata(pdev, provider);
+
+	return 0;
+err:
+	icc_nodes_remove(provider);
+	icc_provider_del(provider);
+	return ret;
+}
+
+static int emi_icc_remove(struct platform_device *pdev)
+{
+	struct icc_provider *provider = platform_get_drvdata(pdev);
+
+	icc_nodes_remove(provider);
+	return icc_provider_del(provider);
+}
+
+static struct platform_driver emi_icc_driver = {
+	.probe = emi_icc_probe,
+	.remove = emi_icc_remove,
+	.driver = {
+		.name = "mediatek-emi-icc",
+	},
+};
+
+static int __init mtk_emi_icc_init(void)
+{
+	return platform_driver_register(&emi_icc_driver);
+}
+subsys_initcall(mtk_emi_icc_init);
+
+static void __exit mtk_emi_icc_exit(void)
+{
+	platform_driver_unregister(&emi_icc_driver);
+}
+module_exit(mtk_emi_icc_exit);
+
+MODULE_AUTHOR("Henry Chen <henryc.chen@mediatek.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 13/19] interconnect: mediatek: add support for mt8195
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (11 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 12/19] interconnect: mediatek: Add interconnect provider driver Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2022-02-03 15:19   ` AngeloGioacchino Del Regno
  2021-08-12  8:58 ` [V11,PATCH 14/19] interconnect: mediatek: add initial bandwidth Dawei Chien
                   ` (5 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien

add platform data of mt8195

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 drivers/interconnect/mediatek/mtk-emi.c | 51 +++++++++++++++++++++++++++++++--
 1 file changed, 48 insertions(+), 3 deletions(-)

diff --git a/drivers/interconnect/mediatek/mtk-emi.c b/drivers/interconnect/mediatek/mtk-emi.c
index 8d650be62b90..379dab77ebfd 100644
--- a/drivers/interconnect/mediatek/mtk-emi.c
+++ b/drivers/interconnect/mediatek/mtk-emi.c
@@ -12,6 +12,7 @@
 #include <linux/soc/mediatek/mtk_dvfsrc.h>
 #include <dt-bindings/interconnect/mtk,mt6873-emi.h>
 #include <dt-bindings/interconnect/mtk,mt8183-emi.h>
+#include <dt-bindings/interconnect/mtk,mt8195-emi.h>
 
 enum mtk_icc_name {
 	SLAVE_DDR_EMI,
@@ -31,7 +32,8 @@ enum mtk_icc_name {
 	MASTER_MDLASYS,
 	MASTER_MDLA_PORT_0,
 	MASTER_UFS,
-	MASTER_PCIE,
+	MASTER_PCIE_0,
+	MASTER_PCIE_1,
 	MASTER_USB,
 	MASTER_WIFI,
 	MASTER_BT,
@@ -102,7 +104,8 @@ DEFINE_MNODE(vpu_port_1, MASTER_VPU_PORT_1, 0, MASTER_VPUSYS);
 DEFINE_MNODE(mdlasys, MASTER_MDLASYS, 0, SLAVE_DDR_EMI);
 DEFINE_MNODE(mdla_port_0, MASTER_MDLA_PORT_0, 0, MASTER_MDLASYS);
 DEFINE_MNODE(ufs, MASTER_UFS, 0, SLAVE_DDR_EMI);
-DEFINE_MNODE(pcie, MASTER_PCIE, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(pcie_0, MASTER_PCIE_0, 0, SLAVE_DDR_EMI);
+DEFINE_MNODE(pcie_1, MASTER_PCIE_1, 0, SLAVE_DDR_EMI);
 DEFINE_MNODE(usb, MASTER_USB, 0, SLAVE_DDR_EMI);
 DEFINE_MNODE(wifi, MASTER_WIFI, 0, SLAVE_DDR_EMI);
 DEFINE_MNODE(bt, MASTER_BT, 0, SLAVE_DDR_EMI);
@@ -156,7 +159,7 @@ static struct mtk_icc_node *mt6873_icc_nodes[] = {
 	[MT6873_MASTER_MDLASYS] = &mdlasys,
 	[MT6873_MASTER_MDLA_0] = &mdla_port_0,
 	[MT6873_MASTER_UFS] = &ufs,
-	[MT6873_MASTER_PCIE] = &pcie,
+	[MT6873_MASTER_PCIE] = &pcie_0,
 	[MT6873_MASTER_USB] = &usb,
 	[MT6873_MASTER_WIFI] = &wifi,
 	[MT6873_MASTER_BT] = &bt,
@@ -179,10 +182,52 @@ static struct mtk_icc_desc mt6873_icc = {
 	.num_nodes = ARRAY_SIZE(mt6873_icc_nodes),
 };
 
+static struct mtk_icc_node *mt8195_icc_nodes[] = {
+	[MT8195_SLAVE_DDR_EMI] = &ddr_emi,
+	[MT8195_MASTER_MCUSYS] = &mcusys,
+	[MT8195_MASTER_GPUSYS] = &gpu,
+	[MT8195_MASTER_MMSYS] = &mmsys,
+	[MT8195_MASTER_MM_VPU] = &mm_vpu,
+	[MT8195_MASTER_MM_DISP] = &mm_disp,
+	[MT8195_MASTER_MM_VDEC] = &mm_vdec,
+	[MT8195_MASTER_MM_VENC] = &mm_venc,
+	[MT8195_MASTER_MM_CAM] = &mm_cam,
+	[MT8195_MASTER_MM_IMG] = &mm_img,
+	[MT8195_MASTER_MM_MDP] = &mm_mdp,
+	[MT8195_MASTER_VPUSYS] = &vpusys,
+	[MT8195_MASTER_VPU_0] = &vpu_port_0,
+	[MT8195_MASTER_VPU_1] = &vpu_port_1,
+	[MT8195_MASTER_MDLASYS] = &mdlasys,
+	[MT8195_MASTER_MDLA_0] = &mdla_port_0,
+	[MT8195_MASTER_UFS] = &ufs,
+	[MT8195_MASTER_PCIE_0] = &pcie_0,
+	[MT8195_MASTER_PCIE_1] = &pcie_1,
+	[MT8195_MASTER_USB] = &usb,
+	[MT8195_MASTER_WIFI] = &wifi,
+	[MT8195_MASTER_BT] = &bt,
+	[MT8195_MASTER_NETSYS] = &netsys,
+	[MT8195_MASTER_DBGIF] = &dbgif,
+	[MT8195_SLAVE_HRT_DDR_EMI] = &hrt_ddr_emi,
+	[MT8195_MASTER_HRT_MMSYS] = &hrt_mmsys,
+	[MT8195_MASTER_HRT_MM_DISP] = &hrt_mm_disp,
+	[MT8195_MASTER_HRT_MM_VDEC] = &hrt_mm_vdec,
+	[MT8195_MASTER_HRT_MM_VENC] = &hrt_mm_venc,
+	[MT8195_MASTER_HRT_MM_CAM] = &hrt_mm_cam,
+	[MT8195_MASTER_HRT_MM_IMG] = &hrt_mm_img,
+	[MT8195_MASTER_HRT_MM_MDP] = &hrt_mm_mdp,
+	[MT8195_MASTER_HRT_DBGIF] = &hrt_dbgif,
+};
+
+static struct mtk_icc_desc mt8195_icc = {
+	.nodes = mt8195_icc_nodes,
+	.num_nodes = ARRAY_SIZE(mt8195_icc_nodes),
+};
+
 static const struct of_device_id emi_icc_of_match[] = {
 	{ .compatible = "mediatek,mt8183-dvfsrc", .data = &mt8183_icc },
 	{ .compatible = "mediatek,mt8192-dvfsrc", .data = &mt6873_icc },
 	{ .compatible = "mediatek,mt6873-dvfsrc", .data = &mt6873_icc },
+	{ .compatible = "mediatek,mt8195-dvfsrc", .data = &mt8195_icc },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, emi_icc_of_match);
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 14/19] interconnect: mediatek: add initial bandwidth
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (12 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 13/19] interconnect: mediatek: add support for mt8195 Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 15/19] regulator: mediatek: add support for mt8195 Dawei Chien
                   ` (4 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien

support get_bw function for suitable initial bandwidth

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 drivers/interconnect/mediatek/mtk-emi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/interconnect/mediatek/mtk-emi.c b/drivers/interconnect/mediatek/mtk-emi.c
index 379dab77ebfd..80e2707698be 100644
--- a/drivers/interconnect/mediatek/mtk-emi.c
+++ b/drivers/interconnect/mediatek/mtk-emi.c
@@ -271,6 +271,14 @@ static int emi_icc_set(struct icc_node *src, struct icc_node *dst)
 	return ret;
 }
 
+static int emi_icc_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
+{
+	*avg = 0;
+	*peak = 0;
+
+	return 0;
+}
+
 static int emi_icc_remove(struct platform_device *pdev);
 static int emi_icc_probe(struct platform_device *pdev)
 {
@@ -308,6 +316,7 @@ static int emi_icc_probe(struct platform_device *pdev)
 	provider->set = emi_icc_set;
 	provider->aggregate = emi_icc_aggregate;
 	provider->xlate = of_icc_xlate_onecell;
+	provider->get_bw = emi_icc_get_bw;
 	INIT_LIST_HEAD(&provider->nodes);
 	provider->data = data;
 
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 15/19] regulator: mediatek: add support for mt8195
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (13 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 14/19] interconnect: mediatek: add initial bandwidth Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2022-02-03 15:21   ` AngeloGioacchino Del Regno
  2021-08-12  8:58 ` [V11,PATCH 16/19] arm64: dts: mt8183: add dvfsrc related nodes Dawei Chien
                   ` (3 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien

add platform data on mt8195

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 drivers/regulator/mtk-dvfsrc-regulator.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/regulator/mtk-dvfsrc-regulator.c b/drivers/regulator/mtk-dvfsrc-regulator.c
index d3d876198d6e..1bd6e67b1de5 100644
--- a/drivers/regulator/mtk-dvfsrc-regulator.c
+++ b/drivers/regulator/mtk-dvfsrc-regulator.c
@@ -140,6 +140,25 @@ static const struct dvfsrc_regulator_init_data regulator_mt6873_data = {
 	.regulator_info = &mt6873_regulators[0],
 };
 
+static const unsigned int mt8195_voltages[] = {
+	550000,
+	600000,
+	650000,
+	750000,
+};
+
+static struct dvfsrc_regulator mt8195_regulators[] = {
+	MT_DVFSRC_REGULAR("dvfsrc-vcore", VCORE,
+			  mt8195_voltages),
+	MT_DVFSRC_REGULAR("dvfsrc-vscp", VSCP,
+			  mt8195_voltages),
+};
+
+static const struct dvfsrc_regulator_init_data regulator_mt8195_data = {
+	.size = ARRAY_SIZE(mt8195_regulators),
+	.regulator_info = &mt8195_regulators[0],
+};
+
 static const struct of_device_id mtk_dvfsrc_regulator_match[] = {
 	{
 		.compatible = "mediatek,mt8183-dvfsrc",
@@ -150,6 +169,10 @@ static const struct of_device_id mtk_dvfsrc_regulator_match[] = {
 	}, {
 		.compatible = "mediatek,mt6873-dvfsrc",
 		.data = &regulator_mt6873_data,
+	}, {
+		.compatible = "mediatek,mt8195-dvfsrc",
+		.data = &regulator_mt8195_data,
+	}, {
 	}, {
 		/* sentinel */
 	},
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 16/19] arm64: dts: mt8183: add dvfsrc related nodes
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (14 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 15/19] regulator: mediatek: add support for mt8195 Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2022-02-03 15:16   ` AngeloGioacchino Del Regno
  2021-08-12  8:58 ` [V11,PATCH 17/19] arm64: dts: mt8192: " Dawei Chien
                   ` (2 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

Add DDR EMI provider dictating dram interconnect bus performance found on
MT8192-based platforms

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 7ad4cf646579..86f85c34c88a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/clock/mt8183-clk.h>
 #include <dt-bindings/gce/mt8183-gce.h>
+#include <dt-bindings/interconnect/mtk,mt8183-emi.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/memory/mt8183-larb-port.h>
@@ -586,6 +587,7 @@
 		ddr_emi: dvfsrc@10012000 {
 			compatible = "mediatek,mt8183-dvfsrc";
 			reg = <0 0x10012000 0 0x1000>;
+			#interconnect-cells = <1>;
 		};
 
 		pwrap: pwrap@1000d000 {
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 17/19] arm64: dts: mt8192: add dvfsrc related nodes
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (15 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 16/19] arm64: dts: mt8183: add dvfsrc related nodes Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 18/19] arm64: dts: mt8192: add dvfsrc regulator nodes Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 19/19] arm64: dts: mt8195: add dvfsrc related nodes Dawei Chien
  18 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

Add DDR EMI provider dictating dram interconnect bus performance found on
MT8183-based platforms

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c70a3bf744fa..ab3dabcc722e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -5,6 +5,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/interconnect/mtk,mt6873-emi.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
@@ -286,6 +287,7 @@
 			compatible = "mediatek,mt8192-dvfsrc",
 				     "mediatek,mt6873-dvfsrc";
 			reg = <0 0x10012000 0 0x1000>;
+			#interconnect-cells = <1>;
 		};
 
 		systimer: timer@10017000 {
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 18/19] arm64: dts: mt8192: add dvfsrc regulator nodes
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (16 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 17/19] arm64: dts: mt8192: " Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  2021-08-12  8:58 ` [V11,PATCH 19/19] arm64: dts: mt8195: add dvfsrc related nodes Dawei Chien
  18 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien, Henry Chen

From: Henry Chen <henryc.chen@mediatek.com>

Add dvfsrc regulator nodes which is for MT8192-based platforms

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index ab3dabcc722e..6aad5ff0646c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -288,6 +288,12 @@
 				     "mediatek,mt6873-dvfsrc";
 			reg = <0 0x10012000 0 0x1000>;
 			#interconnect-cells = <1>;
+			dvfsrc_vcore: dvfsrc-vcore {
+				regulator-name = "dvfsrc-vcore";
+				regulator-min-microvolt = <575000>;
+				regulator-max-microvolt = <725000>;
+				regulator-always-on;
+			};
 		};
 
 		systimer: timer@10017000 {
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [V11,PATCH 19/19] arm64: dts: mt8195: add dvfsrc related nodes
  2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
                   ` (17 preceding siblings ...)
  2021-08-12  8:58 ` [V11,PATCH 18/19] arm64: dts: mt8192: add dvfsrc regulator nodes Dawei Chien
@ 2021-08-12  8:58 ` Dawei Chien
  18 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2021-08-12  8:58 UTC (permalink / raw)
  To: Georgi Djakov, Rob Herring, Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Dawei Chien

Add DDR EMI provider dictating dram interconnect bus performance
found on MT8195-based platforms

Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 19430f324ee1..b010aed83906 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/interconnect/mtk,mt8195-emi.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/power/mt8195-power.h>
@@ -689,6 +690,7 @@
 		ddr_emi: dvfsrc@10012000 {
 			compatible = "mediatek,mt8195-dvfsrc";
 			reg = <0 0x10012000 0 0x1000>;
+			#interconnect-cells = <1>;
 		};
 
 		systimer: timer@10017000 {
-- 
2.14.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 02/19] dt-bindings: mediatek: add compatible for MT8195 dvfsrc
  2021-08-12  8:58 ` [V11,PATCH 02/19] dt-bindings: mediatek: add compatible for MT8195 dvfsrc Dawei Chien
@ 2021-08-17 21:23   ` Rob Herring
  0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2021-08-17 21:23 UTC (permalink / raw)
  To: Dawei Chien
  Cc: Georgi Djakov, Ryan Case, Rob Herring, Arvin Wang, devicetree,
	linux-mediatek, Mark Rutland, James Liao, Nicolas Boichat,
	linux-pm, linux-arm-kernel, Fan Chen, linux-kernel, Stephen Boyd,
	Matthias Brugger

On Thu, 12 Aug 2021 16:58:29 +0800, Dawei Chien wrote:
> This adds dt-binding documentation of dvfsrc for Mediatek MT8195
> SoCs Platform.
> 
> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> ---
>  Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 11/19] dt-bindings: interconnect: add MT8195 interconnect dt-bindings
  2021-08-12  8:58 ` [V11,PATCH 11/19] dt-bindings: interconnect: add MT8195 " Dawei Chien
@ 2021-08-17 21:24   ` Rob Herring
  2022-02-03 15:22   ` [V11, PATCH " AngeloGioacchino Del Regno
  1 sibling, 0 replies; 36+ messages in thread
From: Rob Herring @ 2021-08-17 21:24 UTC (permalink / raw)
  To: Dawei Chien
  Cc: Fan Chen, Mark Rutland, Ryan Case, linux-arm-kernel, Rob Herring,
	Matthias Brugger, linux-mediatek, Arvin Wang, linux-pm,
	devicetree, James Liao, Stephen Boyd, Nicolas Boichat,
	linux-kernel, Georgi Djakov

On Thu, 12 Aug 2021 16:58:38 +0800, Dawei Chien wrote:
> Add interconnect provider dt-bindings for MT8195
> 
> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> ---
>  include/dt-bindings/interconnect/mtk,mt8195-emi.h | 42 +++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
>  create mode 100644 include/dt-bindings/interconnect/mtk,mt8195-emi.h
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 04/19] soc: mediatek: add driver for dvfsrc support
  2021-08-12  8:58 ` [V11,PATCH 04/19] soc: mediatek: add driver for dvfsrc support Dawei Chien
@ 2022-02-03 15:04   ` AngeloGioacchino Del Regno
  2022-02-11  3:51     ` Dawei Chien
  0 siblings, 1 reply; 36+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-03 15:04 UTC (permalink / raw)
  To: Dawei Chien, Georgi Djakov, Rob Herring, Matthias Brugger,
	Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

Il 12/08/21 10:58, Dawei Chien ha scritto:
> From: Henry Chen <henryc.chen@mediatek.com>
> 
> Add dvfsrc driver for MT6873/MT8183/MT8192
> 
> Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> ---
>   drivers/soc/mediatek/Kconfig            |  11 +
>   drivers/soc/mediatek/Makefile           |   1 +
>   drivers/soc/mediatek/mtk-dvfsrc.c       | 421 ++++++++++++++++++++++++++++++++
>   include/linux/soc/mediatek/mtk_dvfsrc.h |  35 +++
>   4 files changed, 468 insertions(+)
>   create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
>   create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h
> 
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index fdd8bc08569e..2dcf02384639 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -26,6 +26,17 @@ config MTK_DEVAPC
>   	  The violation information is logged for further analysis or
>   	  countermeasures.
>   
> +config MTK_DVFSRC
> +	tristate "MediaTek DVFSRC Support"
> +	depends on ARCH_MEDIATEK
> +	help
> +	  Say yes here to add support for the MediaTek DVFSRC (dynamic voltage
> +	  and frequency scaling resource collector) found
> +	  on different MediaTek SoCs. The DVFSRC is a proprietary
> +	  hardware which is used to collect all the requests from
> +	  system and turn into the decision of minimum Vcore voltage
> +	  and minimum DRAM frequency to fulfill those requests.
> +
>   config MTK_INFRACFG
>   	bool "MediaTek INFRACFG Support"
>   	select REGMAP
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 90270f8114ed..365d14fd7d49 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -1,6 +1,7 @@
>   # SPDX-License-Identifier: GPL-2.0-only
>   obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
>   obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o
> +obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
>   obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>   obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>   obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c b/drivers/soc/mediatek/mtk-dvfsrc.c
> new file mode 100644
> index 000000000000..6ef167cf55bd
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-dvfsrc.c
> @@ -0,0 +1,421 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/arm-smccc.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/notifier.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk_dvfsrc.h>
> +#include <linux/soc/mediatek/mtk_sip_svc.h>
> +
> +#define DVFSRC_IDLE     0x00
> +#define DVFSRC_GET_TARGET_LEVEL(x)  (((x) >> 0) & 0x0000ffff)
> +#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x0000ffff)
> +#define kbps_to_mbps(x) ((x) / 1000)
> +
> +#define POLL_TIMEOUT        1000
> +#define STARTUP_TIME        1
> +
> +#define MTK_SIP_DVFSRC_INIT		0x00
> +
> +#define DVFSRC_OPP_DESC(_opp_table)	\
> +{	\
> +	.opps = _opp_table,	\
> +	.num_opp = ARRAY_SIZE(_opp_table),	\
> +}
> +
> +struct dvfsrc_opp {
> +	u32 vcore_opp;
> +	u32 dram_opp;
> +};
> +
> +struct dvfsrc_opp_desc {
> +	const struct dvfsrc_opp *opps;
> +	u32 num_opp;
> +};
> +
> +struct mtk_dvfsrc;
> +struct dvfsrc_soc_data {
> +	const int *regs;
> +	const struct dvfsrc_opp_desc *opps_desc;
> +	int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
> +	int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
> +	u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc);
> +	u32 (*get_vcp_level)(struct mtk_dvfsrc *dvfsrc);
> +	void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
> +	void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
> +	void (*set_dram_hrtbw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
> +	void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
> +	void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
> +	void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
> +	int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
> +	int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
> +};
> +
> +struct mtk_dvfsrc {
> +	struct device *dev;
> +	struct platform_device *icc;
> +	struct platform_device *regulator;
> +	const struct dvfsrc_soc_data *dvd;
> +	int dram_type;
> +	const struct dvfsrc_opp_desc *curr_opps;
> +	void __iomem *regs;
> +	spinlock_t req_lock;
> +	struct mutex pstate_lock;
> +	struct notifier_block scpsys_notifier;
> +};
> +
> +static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
> +{
> +	return readl(dvfs->regs + dvfs->dvd->regs[offset]);
> +}
> +
> +static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32 val)
> +{
> +	writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
> +}
> +
> +#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \
> +	dvfsrc_write(dvfs, offset, \
> +		(dvfsrc_read(dvfs, offset) & ~(mask << shift)) | (val << shift))
> +

Hello Dawei,

is there any reason why you're not using regmap-mmio here?
If your concern is about regmap locking overhead, you can disable it by
setting disable_locking as true in the regmap_config.

> +enum dvfsrc_regs {
> +	DVFSRC_SW_REQ,
> +	DVFSRC_SW_REQ2,
> +	DVFSRC_LEVEL,
> +	DVFSRC_TARGET_LEVEL,
> +	DVFSRC_SW_BW,
> +	DVFSRC_SW_PEAK_BW,
> +	DVFSRC_SW_HRT_BW,
> +	DVFSRC_VCORE_REQUEST,
> +};
> +
> +static const int mt8183_regs[] = {
> +	[DVFSRC_SW_REQ] =	0x4,
> +	[DVFSRC_SW_REQ2] =	0x8,
> +	[DVFSRC_LEVEL] =	0xDC,
> +	[DVFSRC_SW_BW] =	0x160,
> +};
> +
> +static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc *dvfsrc)
> +{
> +	int level;

	int level = dvfsrc->dvd->get_current_level(dvfsrc);

> +
> +	level = dvfsrc->dvd->get_current_level(dvfsrc);
> +	return &dvfsrc->curr_opps->opps[level];
> +}
> +
> +static int dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc)
> +{
> +	if (!dvfsrc->dvd->get_target_level)
> +		return true;
> +
> +	return dvfsrc->dvd->get_target_level(dvfsrc);
> +}
> +
> +static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level)
> +{
> +	const struct dvfsrc_opp *curr;
> +
> +	return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr,
> +					 curr->vcore_opp >= level, STARTUP_TIME,
> +					 POLL_TIMEOUT);
> +}
> +
> +static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
> +{
> +	const struct dvfsrc_opp *target, *curr;
> +	int ret;
> +
> +	target = &dvfsrc->curr_opps->opps[level];
> +	ret = readx_poll_timeout(get_current_opp, dvfsrc, curr,
> +				 curr->dram_opp >= target->dram_opp &&
> +				 curr->vcore_opp >= target->vcore_opp,
> +				 STARTUP_TIME, POLL_TIMEOUT);
> +	if (ret < 0) {
> +		dev_warn(dvfsrc->dev,
> +			 "timeout, target: %u, dram: %d, vcore: %d\n", level,
> +			 curr->dram_opp, curr->vcore_opp);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int mt8183_get_target_level(struct mtk_dvfsrc *dvfsrc)
> +{
> +	return DVFSRC_GET_TARGET_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL));
> +}
> +
> +static int mt8183_get_current_level(struct mtk_dvfsrc *dvfsrc)
> +{
> +	int level;
> +
> +	/* HW level 0 is begin from 0x10000 */
> +	level = DVFSRC_GET_CURRENT_LEVEL(dvfsrc_read(dvfsrc, DVFSRC_LEVEL));
> +	/* Array index start from 0 */
> +	return ffs(level) - 1;
> +}
> +
> +static u32 mt8183_get_vcore_level(struct mtk_dvfsrc *dvfsrc)
> +{
> +	return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ2) >> 2) & 0x3;
> +}
> +
> +static void mt8183_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
> +{

Is there any min/max allowed bw? If there is, please add a boudary check here.
Same for set_vcore_level.

> +	dvfsrc_write(dvfsrc, DVFSRC_SW_BW, div_u64(kbps_to_mbps(bw), 100));
> +}
> +
> +static void mt8183_set_opp_level(struct mtk_dvfsrc *dvfsrc, u32 level)
> +{
> +	int vcore_opp, dram_opp;
> +	const struct dvfsrc_opp *opp;
> +
> +	/* translate pstate to dvfsrc level, and set it to DVFSRC HW */
> +	opp = &dvfsrc->curr_opps->opps[level];
> +	vcore_opp = opp->vcore_opp;
> +	dram_opp = opp->dram_opp;
> +
> +	dev_dbg(dvfsrc->dev, "vcore_opp: %d, dram_opp: %d\n",
> +		vcore_opp, dram_opp);
> +	dvfsrc_write(dvfsrc, DVFSRC_SW_REQ, dram_opp | vcore_opp << 2);
> +}
> +
> +static void mt8183_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32 level)
> +{
> +	dvfsrc_write(dvfsrc, DVFSRC_SW_REQ2, level << 2);
> +}
> +
> +void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data)

int mtk_dvfsrc_send_request(......

> +{
> +	int ret, state;
> +	struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev);
> +
> +	dev_dbg(dvfsrc->dev, "cmd: %d, data: %llu\n", cmd, data);
> +
> +	switch (cmd) {
> +	case MTK_DVFSRC_CMD_BW_REQUEST:
> +		dvfsrc->dvd->set_dram_bw(dvfsrc, data);
> +		return;
> +	case MTK_DVFSRC_CMD_PEAK_BW_REQUEST:
> +		if (dvfsrc->dvd->set_dram_peak_bw)
> +			dvfsrc->dvd->set_dram_peak_bw(dvfsrc, data);
> +		return;
> +	case MTK_DVFSRC_CMD_OPP_REQUEST:
> +		if (dvfsrc->dvd->set_opp_level)
> +			dvfsrc->dvd->set_opp_level(dvfsrc, data);
> +		break;
> +	case MTK_DVFSRC_CMD_VCORE_REQUEST:
> +		dvfsrc->dvd->set_vcore_level(dvfsrc, data);
> +		break;
> +	case MTK_DVFSRC_CMD_HRTBW_REQUEST:
> +		if (dvfsrc->dvd->set_dram_hrtbw)
> +			dvfsrc->dvd->set_dram_hrtbw(dvfsrc, data);
> +		else
> +			return;

			return -EINVAL;

> +		break;
> +	case MTK_DVFSRC_CMD_VSCP_REQUEST:
> +		dvfsrc->dvd->set_vscp_level(dvfsrc, data);
> +		break;
> +	default:
> +		dev_err(dvfsrc->dev, "unknown command: %d\n", cmd);
> +		return;

		return -EINVAL;

> +	}
> +
> +	/* DVFSRC needs to wait at least 2T(~196ns) to handle request
> +	 * after receiving command
> +	 */
> +	udelay(STARTUP_TIME);
> +
> +	ret = readx_poll_timeout(dvfsrc_is_idle, dvfsrc,
> +				 state, state == DVFSRC_IDLE,
> +				 STARTUP_TIME, POLL_TIMEOUT);
> +
> +	if (ret < 0) {
> +		dev_warn(dvfsrc->dev,
> +			 "%d: idle timeout, data: %llu, last: %d -> %d\n",
> +			 cmd, data,
> +			 dvfsrc->dvd->get_current_level(dvfsrc),
> +			 dvfsrc->dvd->get_target_level(dvfsrc));
> +		return;

		return ret;

> +	}
> +
> +	/* The previous change may be requested by previous request.
> +	 * So we delay 1us, then start checking opp is reached enough.
> +	 */
> +	udelay(STARTUP_TIME);
> +
> +	if (cmd == MTK_DVFSRC_CMD_OPP_REQUEST)
> +		ret = dvfsrc->dvd->wait_for_opp_level(dvfsrc, data);
> +	else
> +		ret = dvfsrc->dvd->wait_for_vcore_level(dvfsrc, data);
> +
> +	if (ret < 0) {
> +		dev_warn(dvfsrc->dev,
> +			 "%d: wait timeout, data: %llu, last: %d -> %d\n",
> +			 cmd, data,
> +			 dvfsrc->dvd->get_current_level(dvfsrc),
> +			 dvfsrc->dvd->get_target_level(dvfsrc));
> +	}
> +
> +}
> +EXPORT_SYMBOL(mtk_dvfsrc_send_request);
> +
> +int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data)
> +{
> +	struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev);
> +
> +	switch (cmd) {
> +	case MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY:
> +		*data = dvfsrc->dvd->get_vcore_level(dvfsrc);
> +		break;
> +	case MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY:
> +		*data = dvfsrc->dvd->get_vcp_level(dvfsrc);
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(mtk_dvfsrc_query_info);
> +
> +static int mtk_dvfsrc_probe(struct platform_device *pdev)
> +{
> +	struct arm_smccc_res ares;
> +	struct resource *res;
> +	struct mtk_dvfsrc *dvfsrc;
> +	int ret;
> +
> +	dvfsrc = devm_kzalloc(&pdev->dev, sizeof(*dvfsrc), GFP_KERNEL);
> +	if (!dvfsrc)
> +		return -ENOMEM;
> +
> +	dvfsrc->dvd = of_device_get_match_data(&pdev->dev);
> +	dvfsrc->dev = &pdev->dev;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	dvfsrc->regs = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(dvfsrc->regs))
> +		return PTR_ERR(dvfsrc->regs);
> +
> +	spin_lock_init(&dvfsrc->req_lock);
> +	mutex_init(&dvfsrc->pstate_lock);
> +
> +	arm_smccc_smc(MTK_SIP_VCOREFS_CONTROL, MTK_SIP_DVFSRC_INIT, 0, 0, 0,
> +		0, 0, 0, &ares);
> +
> +	if (!ares.a0) {
> +		dvfsrc->dram_type = ares.a1;
> +		dev_info(dvfsrc->dev, "dram_type: %d\n", dvfsrc->dram_type);
> +	} else {
> +		dev_err(dvfsrc->dev, "init fails: %lu\n", ares.a0);
> +		return ares.a0;
> +	}
> +
> +	dvfsrc->curr_opps = &dvfsrc->dvd->opps_desc[dvfsrc->dram_type];
> +	platform_set_drvdata(pdev, dvfsrc);
> +
> +	dvfsrc->regulator = platform_device_register_data(dvfsrc->dev,
> +			"mtk-dvfsrc-regulator", -1, NULL, 0);

Why are you registering platform devices like this?

Please use device-tree instead.

> +	if (IS_ERR(dvfsrc->regulator)) {
> +		dev_err(dvfsrc->dev, "Failed create regulator device\n");
> +		ret = PTR_ERR(dvfsrc->regulator);
> +		goto err;
> +	}
> +
> +	dvfsrc->icc = platform_device_register_data(dvfsrc->dev,
> +			"mediatek-emi-icc", -1, NULL, 0);

Same here.

> +	if (IS_ERR(dvfsrc->icc)) {
> +		dev_err(dvfsrc->dev, "Failed create icc device\n");

As a side note, after applying the suggested flow, you will also be able
to use dev_err_probe() instead, simplifying this probe function.

> +		ret = PTR_ERR(dvfsrc->icc);
> +		goto unregister_regulator;
> +	}
> +
> +	ret = devm_of_platform_populate(&pdev->dev);
> +	if (ret)
> +		platform_device_unregister(dvfsrc->icc);
> +
> +	return 0;
> +
> +unregister_regulator:
> +	platform_device_unregister(dvfsrc->regulator);
> +err:
> +	return ret;
> +}
> +
> +static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp4[] = {
> +	{0, 0}, {0, 1}, {0, 2}, {1, 2},
> +};
> +
> +static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp3[] = {
> +	{0, 0}, {0, 1}, {1, 1}, {1, 2},
> +};
> +
> +static const struct dvfsrc_opp_desc dvfsrc_opp_mt8183_desc[] = {
> +	DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp4),
> +	DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp3),
> +	DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp3),
> +};
> +
> +static const struct dvfsrc_soc_data mt8183_data = {
> +	.opps_desc = dvfsrc_opp_mt8183_desc,
> +	.regs = mt8183_regs,
> +	.get_target_level = mt8183_get_target_level,
> +	.get_current_level = mt8183_get_current_level,
> +	.get_vcore_level = mt8183_get_vcore_level,
> +	.set_dram_bw = mt8183_set_dram_bw,
> +	.set_opp_level = mt8183_set_opp_level,
> +	.set_vcore_level = mt8183_set_vcore_level,
> +	.wait_for_opp_level = mt8183_wait_for_opp_level,
> +	.wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
> +};
> +
> +static int mtk_dvfsrc_remove(struct platform_device *pdev)
> +{
> +	struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev);
> +
> +	platform_device_unregister(dvfsrc->regulator);
> +	platform_device_unregister(dvfsrc->icc);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id mtk_dvfsrc_of_match[] = {
> +	{
> +		.compatible = "mediatek,mt8183-dvfsrc",
> +		.data = &mt8183_data,
> +	}, {
> +		/* sentinel */
> +	},
> +};
> +
> +static struct platform_driver mtk_dvfsrc_driver = {
> +	.probe	= mtk_dvfsrc_probe,
> +	.remove	= mtk_dvfsrc_remove,
> +	.driver = {
> +		.name = "mtk-dvfsrc",
> +		.of_match_table = of_match_ptr(mtk_dvfsrc_of_match),
> +	},
> +};
> +
> +static int __init mtk_dvfsrc_init(void)
> +{
> +	return platform_driver_register(&mtk_dvfsrc_driver);
> +}
> +subsys_initcall(mtk_dvfsrc_init);
> +
> +static void __exit mtk_dvfsrc_exit(void)
> +{
> +	platform_driver_unregister(&mtk_dvfsrc_driver);
> +}
> +module_exit(mtk_dvfsrc_exit);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("MTK DVFSRC driver");
> diff --git a/include/linux/soc/mediatek/mtk_dvfsrc.h b/include/linux/soc/mediatek/mtk_dvfsrc.h
> new file mode 100644
> index 000000000000..823eff9bb19f
> --- /dev/null
> +++ b/include/linux/soc/mediatek/mtk_dvfsrc.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __SOC_MTK_DVFSRC_H
> +#define __SOC_MTK_DVFSRC_H
> +
> +#define MTK_DVFSRC_CMD_BW_REQUEST		0
> +#define MTK_DVFSRC_CMD_OPP_REQUEST		1
> +#define MTK_DVFSRC_CMD_VCORE_REQUEST		2
> +#define MTK_DVFSRC_CMD_HRTBW_REQUEST		3
> +#define MTK_DVFSRC_CMD_VSCP_REQUEST		4
> +#define MTK_DVFSRC_CMD_PEAK_BW_REQUEST		5
> +
> +#define MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY	0
> +#define MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY		1
> +
> +#if IS_ENABLED(CONFIG_MTK_DVFSRC)
> +void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data);
> +int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data);
> +
> +#else
> +
> +static inline void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd,
> +					   u64 data)
> +{ return -ENODEV; }
> +
> +static inline int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd,
> +					int *data);
> +{ return -ENODEV; }
> +
> +#endif /* CONFIG_MTK_DVFSRC */
> +
> +#endif

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 05/19] soc: mediatek: add support for mt6873
  2021-08-12  8:58 ` [V11,PATCH 05/19] soc: mediatek: add support for mt6873 Dawei Chien
@ 2022-02-03 15:13   ` AngeloGioacchino Del Regno
  2022-02-11  3:50     ` Dawei Chien
  0 siblings, 1 reply; 36+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-03 15:13 UTC (permalink / raw)
  To: Dawei Chien, Georgi Djakov, Rob Herring, Matthias Brugger,
	Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

Il 12/08/21 10:58, Dawei Chien ha scritto:
> From: Henry Chen <henryc.chen@mediatek.com>
> 
> add support for mt6873
> 
> Signed-off-by: Henry Chen <henryc.chen@mediatek.com>

You forgot to add your Signed-off-by tag here. Even if this patch is
not yours, you're the sender, so you have to sign it.

Besides, can you please fix the title?

soc: mediatek: mtk-dvfsrc: Add support for MT6873

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11, PATCH 03/19] soc: mediatek: add header for mediatek SIP interface
  2021-08-12  8:58 ` [V11,PATCH 03/19] soc: mediatek: add header for mediatek SIP interface Dawei Chien
@ 2022-02-03 15:14   ` AngeloGioacchino Del Regno
  2022-02-11  3:50     ` Dawei Chien
  0 siblings, 1 reply; 36+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-03 15:14 UTC (permalink / raw)
  To: Dawei Chien, Georgi Djakov, Rob Herring, Matthias Brugger,
	Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

Il 12/08/21 10:58, Dawei Chien ha scritto:
> From: Henry Chen <henryc.chen@mediatek.com>
> 
> Add a header to collect SIPs and add one SIP call to initialize power
> management hardware for the SIP interface defined to access the SPM
> handling vcore voltage and ddr rate changes on mt8183 (and most likely
> later socs).
> 
> Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
> Signed-off-by: Arvin Wang <arvin.wang@mediatek.com>

Please sign-off this and all the other patches that you send.

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 16/19] arm64: dts: mt8183: add dvfsrc related nodes
  2021-08-12  8:58 ` [V11,PATCH 16/19] arm64: dts: mt8183: add dvfsrc related nodes Dawei Chien
@ 2022-02-03 15:16   ` AngeloGioacchino Del Regno
  2022-02-11  3:50     ` Dawei Chien
  0 siblings, 1 reply; 36+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-03 15:16 UTC (permalink / raw)
  To: Dawei Chien, Georgi Djakov, Rob Herring, Matthias Brugger,
	Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

Il 12/08/21 10:58, Dawei Chien ha scritto:
> From: Henry Chen <henryc.chen@mediatek.com>
> 
> Add DDR EMI provider dictating dram interconnect bus performance found on
> MT8192-based platforms
> 
> Signed-off-by: Henry Chen <henryc.chen@mediatek.com>

This patch definitely has to be squashed with patch 07/19.

Same for patch 17 and 19.

Also, sign-off.

> ---
>   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 7ad4cf646579..86f85c34c88a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -7,6 +7,7 @@
>   
>   #include <dt-bindings/clock/mt8183-clk.h>
>   #include <dt-bindings/gce/mt8183-gce.h>
> +#include <dt-bindings/interconnect/mtk,mt8183-emi.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/memory/mt8183-larb-port.h>
> @@ -586,6 +587,7 @@
>   		ddr_emi: dvfsrc@10012000 {
>   			compatible = "mediatek,mt8183-dvfsrc";
>   			reg = <0 0x10012000 0 0x1000>;
> +			#interconnect-cells = <1>;
>   		};
>   
>   		pwrap: pwrap@1000d000 {

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11, PATCH 12/19] interconnect: mediatek: Add interconnect provider driver
  2021-08-12  8:58 ` [V11,PATCH 12/19] interconnect: mediatek: Add interconnect provider driver Dawei Chien
@ 2022-02-03 15:19   ` AngeloGioacchino Del Regno
  2022-02-11  3:49     ` Dawei Chien
  0 siblings, 1 reply; 36+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-03 15:19 UTC (permalink / raw)
  To: Dawei Chien, Georgi Djakov, Rob Herring, Matthias Brugger,
	Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

Il 12/08/21 10:58, Dawei Chien ha scritto:
> From: Henry Chen <henryc.chen@mediatek.com>
> 
> Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver
> using the interconnect framework.
> 
>               ICC provider         ICC Nodes
>                                ----          ----
>               ---------       |CPU |   |--- |VPU |
>      -----   |         |-----  ----    |     ----
>     |DRAM |--|DRAM     |       ----    |     ----
>     |     |--|scheduler|----- |GPU |   |--- |DISP|
>     |     |--|(EMI)    |       ----    |     ----
>     |     |--|         |       -----   |     ----
>      -----   |         |----- |MMSYS|--|--- |VDEC|
>               ---------        -----   |     ----
>                 /|\                    |     ----
>                  |change DRAM freq     |--- |VENC|
>               ----------               |     ----
>              |  DVFSR   |              |
>              |          |              |     ----
>               ----------               |--- |IMG |
>                                        |     ----
>                                        |     ----
>                                        |--- |CAM |
>                                              ----
> Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
> Reviewed-by: Georgi Djakov <georgi.djakov@linaro.org>

This patch deserves my Reviewed-by tag, but I cannot release that if the
driver is not properly signed-off.

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 13/19] interconnect: mediatek: add support for mt8195
  2021-08-12  8:58 ` [V11,PATCH 13/19] interconnect: mediatek: add support for mt8195 Dawei Chien
@ 2022-02-03 15:19   ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 36+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-03 15:19 UTC (permalink / raw)
  To: Dawei Chien, Georgi Djakov, Rob Herring, Matthias Brugger,
	Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao

Il 12/08/21 10:58, Dawei Chien ha scritto:
> add platform data of mt8195
> 
> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>

Reviewed-by: AngeloGioachino Del Regno <angelogioacchino.delregno@collabora.com>


^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 15/19] regulator: mediatek: add support for mt8195
  2021-08-12  8:58 ` [V11,PATCH 15/19] regulator: mediatek: add support for mt8195 Dawei Chien
@ 2022-02-03 15:21   ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 36+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-03 15:21 UTC (permalink / raw)
  To: Dawei Chien, Georgi Djakov, Rob Herring, Matthias Brugger,
	Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao

Il 12/08/21 10:58, Dawei Chien ha scritto:
> add platform data on mt8195
> 
> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11, PATCH 11/19] dt-bindings: interconnect: add MT8195 interconnect dt-bindings
  2021-08-12  8:58 ` [V11,PATCH 11/19] dt-bindings: interconnect: add MT8195 " Dawei Chien
  2021-08-17 21:24   ` Rob Herring
@ 2022-02-03 15:22   ` AngeloGioacchino Del Regno
  1 sibling, 0 replies; 36+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-03 15:22 UTC (permalink / raw)
  To: Dawei Chien, Georgi Djakov, Rob Herring, Matthias Brugger,
	Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao

Il 12/08/21 10:58, Dawei Chien ha scritto:
> Add interconnect provider dt-bindings for MT8195
> 
> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> Acked-by: Rob Herring <robh@kernel.org>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11, PATCH 12/19] interconnect: mediatek: Add interconnect provider driver
  2022-02-03 15:19   ` [V11, PATCH " AngeloGioacchino Del Regno
@ 2022-02-11  3:49     ` Dawei Chien
  0 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2022-02-11  3:49 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno, Georgi Djakov, Rob Herring,
	Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

On Thu, 2022-02-03 at 16:19 +0100, AngeloGioacchino Del Regno wrote:
> Il 12/08/21 10:58, Dawei Chien ha scritto:
> > From: Henry Chen <henryc.chen@mediatek.com>
> > 
> > Introduce Mediatek MT6873/MT8183/MT8192 specific provider driver
> > using the interconnect framework.
> > 
> >               ICC provider         ICC Nodes
> >                                ----          ----
> >               ---------       |CPU |   |--- |VPU |
> >      -----   |         |-----  ----    |     ----
> >     |DRAM |--|DRAM     |       ----    |     ----
> >     |     |--|scheduler|----- |GPU |   |--- |DISP|
> >     |     |--|(EMI)    |       ----    |     ----
> >     |     |--|         |       -----   |     ----
> >      -----   |         |----- |MMSYS|--|--- |VDEC|
> >               ---------        -----   |     ----
> >                 /|\                    |     ----
> >                  |change DRAM freq     |--- |VENC|
> >               ----------               |     ----
> >              |  DVFSR   |              |
> >              |          |              |     ----
> >               ----------               |--- |IMG |
> >                                        |     ----
> >                                        |     ----
> >                                        |--- |CAM |
> >                                              ----
> > Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
> > Reviewed-by: Georgi Djakov <georgi.djakov@linaro.org>
> 
> This patch deserves my Reviewed-by tag, but I cannot release that if
> the
> driver is not properly signed-off.

I would add singed-off tag on next version, thank you.


^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 16/19] arm64: dts: mt8183: add dvfsrc related nodes
  2022-02-03 15:16   ` AngeloGioacchino Del Regno
@ 2022-02-11  3:50     ` Dawei Chien
  0 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2022-02-11  3:50 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno, Georgi Djakov, Rob Herring,
	Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

On Thu, 2022-02-03 at 16:16 +0100, AngeloGioacchino Del Regno wrote:
> Il 12/08/21 10:58, Dawei Chien ha scritto:
> > From: Henry Chen <henryc.chen@mediatek.com>
> > 
> > Add DDR EMI provider dictating dram interconnect bus performance
> > found on
> > MT8192-based platforms
> > 
> > Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
> 
> This patch definitely has to be squashed with patch 07/19.
> 
> Same for patch 17 and 19.
> 
> Also, sign-off.
> 

I would squash patch 07/16, 08/17, 09/18 on next version, thank you.

> > ---
> >   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 ++
> >   1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index 7ad4cf646579..86f85c34c88a 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -7,6 +7,7 @@
> >   
> >   #include <dt-bindings/clock/mt8183-clk.h>
> >   #include <dt-bindings/gce/mt8183-gce.h>
> > +#include <dt-bindings/interconnect/mtk,mt8183-emi.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >   #include <dt-bindings/interrupt-controller/irq.h>
> >   #include <dt-bindings/memory/mt8183-larb-port.h>
> > @@ -586,6 +587,7 @@
> >   		ddr_emi: dvfsrc@10012000 {
> >   			compatible = "mediatek,mt8183-dvfsrc";
> >   			reg = <0 0x10012000 0 0x1000>;
> > +			#interconnect-cells = <1>;
> >   		};
> >   
> >   		pwrap: pwrap@1000d000 {


^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11, PATCH 03/19] soc: mediatek: add header for mediatek SIP interface
  2022-02-03 15:14   ` [V11, PATCH " AngeloGioacchino Del Regno
@ 2022-02-11  3:50     ` Dawei Chien
  0 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2022-02-11  3:50 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno, Georgi Djakov, Rob Herring,
	Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

On Thu, 2022-02-03 at 16:14 +0100, AngeloGioacchino Del Regno wrote:
> Il 12/08/21 10:58, Dawei Chien ha scritto:
> > From: Henry Chen <henryc.chen@mediatek.com>
> > 
> > Add a header to collect SIPs and add one SIP call to initialize
> > power
> > management hardware for the SIP interface defined to access the SPM
> > handling vcore voltage and ddr rate changes on mt8183 (and most
> > likely
> > later socs).
> > 
> > Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
> > Signed-off-by: Arvin Wang <arvin.wang@mediatek.com>
> 
> Please sign-off this and all the other patches that you send.

Thank you for your review, I would sign-off all the others patches on
next version.


^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 05/19] soc: mediatek: add support for mt6873
  2022-02-03 15:13   ` AngeloGioacchino Del Regno
@ 2022-02-11  3:50     ` Dawei Chien
  0 siblings, 0 replies; 36+ messages in thread
From: Dawei Chien @ 2022-02-11  3:50 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno, Georgi Djakov, Rob Herring,
	Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

On Thu, 2022-02-03 at 16:13 +0100, AngeloGioacchino Del Regno wrote:
> Il 12/08/21 10:58, Dawei Chien ha scritto:
> > From: Henry Chen <henryc.chen@mediatek.com>
> > 
> > add support for mt6873
> > 
> > Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
> 
> You forgot to add your Signed-off-by tag here. Even if this patch is
> not yours, you're the sender, so you have to sign it.
> 
> Besides, can you please fix the title?
> 
> soc: mediatek: mtk-dvfsrc: Add support for MT6873

I would add signed-off tag and fix the title on next version, thank
you.


^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 04/19] soc: mediatek: add driver for dvfsrc support
  2022-02-03 15:04   ` AngeloGioacchino Del Regno
@ 2022-02-11  3:51     ` Dawei Chien
  2022-02-11 11:50       ` AngeloGioacchino Del Regno
  0 siblings, 1 reply; 36+ messages in thread
From: Dawei Chien @ 2022-02-11  3:51 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno, Georgi Djakov, Rob Herring,
	Matthias Brugger, Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

On Thu, 2022-02-03 at 16:04 +0100, AngeloGioacchino Del Regno wrote:
> Il 12/08/21 10:58, Dawei Chien ha scritto:
> > From: Henry Chen <henryc.chen@mediatek.com>
> > 
> > Add dvfsrc driver for MT6873/MT8183/MT8192
> > 
> > Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
> > Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
> > ---
> >   drivers/soc/mediatek/Kconfig            |  11 +
> >   drivers/soc/mediatek/Makefile           |   1 +
> >   drivers/soc/mediatek/mtk-dvfsrc.c       | 421
> > ++++++++++++++++++++++++++++++++
> >   include/linux/soc/mediatek/mtk_dvfsrc.h |  35 +++
> >   4 files changed, 468 insertions(+)
> >   create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
> >   create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h
> > 
> > diff --git a/drivers/soc/mediatek/Kconfig
> > b/drivers/soc/mediatek/Kconfig
> > index fdd8bc08569e..2dcf02384639 100644
> > --- a/drivers/soc/mediatek/Kconfig
> > +++ b/drivers/soc/mediatek/Kconfig
> > @@ -26,6 +26,17 @@ config MTK_DEVAPC
> >   	  The violation information is logged for further analysis or
> >   	  countermeasures.
> >   
> > +config MTK_DVFSRC
> > +	tristate "MediaTek DVFSRC Support"
> > +	depends on ARCH_MEDIATEK
> > +	help
> > +	  Say yes here to add support for the MediaTek DVFSRC (dynamic
> > voltage
> > +	  and frequency scaling resource collector) found
> > +	  on different MediaTek SoCs. The DVFSRC is a proprietary
> > +	  hardware which is used to collect all the requests from
> > +	  system and turn into the decision of minimum Vcore voltage
> > +	  and minimum DRAM frequency to fulfill those requests.
> > +
> >   config MTK_INFRACFG
> >   	bool "MediaTek INFRACFG Support"
> >   	select REGMAP
> > diff --git a/drivers/soc/mediatek/Makefile
> > b/drivers/soc/mediatek/Makefile
> > index 90270f8114ed..365d14fd7d49 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -1,6 +1,7 @@
> >   # SPDX-License-Identifier: GPL-2.0-only
> >   obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> >   obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o
> > +obj-$(CONFIG_MTK_DVFSRC) += mtk-dvfsrc.o
> >   obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> >   obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> >   obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
> > b/drivers/soc/mediatek/mtk-dvfsrc.c
> > new file mode 100644
> > index 000000000000..6ef167cf55bd
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mtk-dvfsrc.c
> > @@ -0,0 +1,421 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <linux/arm-smccc.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/module.h>
> > +#include <linux/notifier.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk_dvfsrc.h>
> > +#include <linux/soc/mediatek/mtk_sip_svc.h>
> > +
> > +#define DVFSRC_IDLE     0x00
> > +#define DVFSRC_GET_TARGET_LEVEL(x)  (((x) >> 0) & 0x0000ffff)
> > +#define DVFSRC_GET_CURRENT_LEVEL(x) (((x) >> 16) & 0x0000ffff)
> > +#define kbps_to_mbps(x) ((x) / 1000)
> > +
> > +#define POLL_TIMEOUT        1000
> > +#define STARTUP_TIME        1
> > +
> > +#define MTK_SIP_DVFSRC_INIT		0x00
> > +
> > +#define DVFSRC_OPP_DESC(_opp_table)	\
> > +{	\
> > +	.opps = _opp_table,	\
> > +	.num_opp = ARRAY_SIZE(_opp_table),	\
> > +}
> > +
> > +struct dvfsrc_opp {
> > +	u32 vcore_opp;
> > +	u32 dram_opp;
> > +};
> > +
> > +struct dvfsrc_opp_desc {
> > +	const struct dvfsrc_opp *opps;
> > +	u32 num_opp;
> > +};
> > +
> > +struct mtk_dvfsrc;
> > +struct dvfsrc_soc_data {
> > +	const int *regs;
> > +	const struct dvfsrc_opp_desc *opps_desc;
> > +	int (*get_target_level)(struct mtk_dvfsrc *dvfsrc);
> > +	int (*get_current_level)(struct mtk_dvfsrc *dvfsrc);
> > +	u32 (*get_vcore_level)(struct mtk_dvfsrc *dvfsrc);
> > +	u32 (*get_vcp_level)(struct mtk_dvfsrc *dvfsrc);
> > +	void (*set_dram_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
> > +	void (*set_dram_peak_bw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
> > +	void (*set_dram_hrtbw)(struct mtk_dvfsrc *dvfsrc, u64 bw);
> > +	void (*set_opp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
> > +	void (*set_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
> > +	void (*set_vscp_level)(struct mtk_dvfsrc *dvfsrc, u32 level);
> > +	int (*wait_for_opp_level)(struct mtk_dvfsrc *dvfsrc, u32
> > level);
> > +	int (*wait_for_vcore_level)(struct mtk_dvfsrc *dvfsrc, u32
> > level);
> > +};
> > +
> > +struct mtk_dvfsrc {
> > +	struct device *dev;
> > +	struct platform_device *icc;
> > +	struct platform_device *regulator;
> > +	const struct dvfsrc_soc_data *dvd;
> > +	int dram_type;
> > +	const struct dvfsrc_opp_desc *curr_opps;
> > +	void __iomem *regs;
> > +	spinlock_t req_lock;
> > +	struct mutex pstate_lock;
> > +	struct notifier_block scpsys_notifier;
> > +};
> > +
> > +static u32 dvfsrc_read(struct mtk_dvfsrc *dvfs, u32 offset)
> > +{
> > +	return readl(dvfs->regs + dvfs->dvd->regs[offset]);
> > +}
> > +
> > +static void dvfsrc_write(struct mtk_dvfsrc *dvfs, u32 offset, u32
> > val)
> > +{
> > +	writel(val, dvfs->regs + dvfs->dvd->regs[offset]);
> > +}
> > +
> > +#define dvfsrc_rmw(dvfs, offset, val, mask, shift) \
> > +	dvfsrc_write(dvfs, offset, \
> > +		(dvfsrc_read(dvfs, offset) & ~(mask << shift)) | (val
> > << shift))
> > +
> 
> Hello Dawei,
> 
> is there any reason why you're not using regmap-mmio here?
> If your concern is about regmap locking overhead, you can disable it
> by
> setting disable_locking as true in the regmap_config.
> 

Thank you for your review, I would use regmap-mmio to access register
on next version.

> > +enum dvfsrc_regs {
> > +	DVFSRC_SW_REQ,
> > +	DVFSRC_SW_REQ2,
> > +	DVFSRC_LEVEL,
> > +	DVFSRC_TARGET_LEVEL,
> > +	DVFSRC_SW_BW,
> > +	DVFSRC_SW_PEAK_BW,
> > +	DVFSRC_SW_HRT_BW,
> > +	DVFSRC_VCORE_REQUEST,
> > +};
> > +
> > +static const int mt8183_regs[] = {
> > +	[DVFSRC_SW_REQ] =	0x4,
> > +	[DVFSRC_SW_REQ2] =	0x8,
> > +	[DVFSRC_LEVEL] =	0xDC,
> > +	[DVFSRC_SW_BW] =	0x160,
> > +};
> > +
> > +static const struct dvfsrc_opp *get_current_opp(struct mtk_dvfsrc
> > *dvfsrc)
> > +{
> > +	int level;
> 
> 	int level = dvfsrc->dvd->get_current_level(dvfsrc);
> 
> > +
> > +	level = dvfsrc->dvd->get_current_level(dvfsrc);
> > +	return &dvfsrc->curr_opps->opps[level];
> > +}
> > +
> > +static int dvfsrc_is_idle(struct mtk_dvfsrc *dvfsrc)
> > +{
> > +	if (!dvfsrc->dvd->get_target_level)
> > +		return true;
> > +
> > +	return dvfsrc->dvd->get_target_level(dvfsrc);
> > +}
> > +
> > +static int dvfsrc_wait_for_vcore_level(struct mtk_dvfsrc *dvfsrc,
> > u32 level)
> > +{
> > +	const struct dvfsrc_opp *curr;
> > +
> > +	return readx_poll_timeout_atomic(get_current_opp, dvfsrc, curr,
> > +					 curr->vcore_opp >= level,
> > STARTUP_TIME,
> > +					 POLL_TIMEOUT);
> > +}
> > +
> > +static int mt8183_wait_for_opp_level(struct mtk_dvfsrc *dvfsrc,
> > u32 level)
> > +{
> > +	const struct dvfsrc_opp *target, *curr;
> > +	int ret;
> > +
> > +	target = &dvfsrc->curr_opps->opps[level];
> > +	ret = readx_poll_timeout(get_current_opp, dvfsrc, curr,
> > +				 curr->dram_opp >= target->dram_opp &&
> > +				 curr->vcore_opp >= target->vcore_opp,
> > +				 STARTUP_TIME, POLL_TIMEOUT);
> > +	if (ret < 0) {
> > +		dev_warn(dvfsrc->dev,
> > +			 "timeout, target: %u, dram: %d, vcore: %d\n",
> > level,
> > +			 curr->dram_opp, curr->vcore_opp);
> > +		return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int mt8183_get_target_level(struct mtk_dvfsrc *dvfsrc)
> > +{
> > +	return DVFSRC_GET_TARGET_LEVEL(dvfsrc_read(dvfsrc,
> > DVFSRC_LEVEL));
> > +}
> > +
> > +static int mt8183_get_current_level(struct mtk_dvfsrc *dvfsrc)
> > +{
> > +	int level;
> > +
> > +	/* HW level 0 is begin from 0x10000 */
> > +	level = DVFSRC_GET_CURRENT_LEVEL(dvfsrc_read(dvfsrc,
> > DVFSRC_LEVEL));
> > +	/* Array index start from 0 */
> > +	return ffs(level) - 1;
> > +}
> > +
> > +static u32 mt8183_get_vcore_level(struct mtk_dvfsrc *dvfsrc)
> > +{
> > +	return (dvfsrc_read(dvfsrc, DVFSRC_SW_REQ2) >> 2) & 0x3;
> > +}
> > +
> > +static void mt8183_set_dram_bw(struct mtk_dvfsrc *dvfsrc, u64 bw)
> > +{
> 
> Is there any min/max allowed bw? If there is, please add a boudary
> check here.
> Same for set_vcore_level.
> 

I would add a boundary check here on next version.

> > +	dvfsrc_write(dvfsrc, DVFSRC_SW_BW, div_u64(kbps_to_mbps(bw),
> > 100));
> > +}
> > +
> > +static void mt8183_set_opp_level(struct mtk_dvfsrc *dvfsrc, u32
> > level)
> > +{
> > +	int vcore_opp, dram_opp;
> > +	const struct dvfsrc_opp *opp;
> > +
> > +	/* translate pstate to dvfsrc level, and set it to DVFSRC HW */
> > +	opp = &dvfsrc->curr_opps->opps[level];
> > +	vcore_opp = opp->vcore_opp;
> > +	dram_opp = opp->dram_opp;
> > +
> > +	dev_dbg(dvfsrc->dev, "vcore_opp: %d, dram_opp: %d\n",
> > +		vcore_opp, dram_opp);
> > +	dvfsrc_write(dvfsrc, DVFSRC_SW_REQ, dram_opp | vcore_opp << 2);
> > +}
> > +
> > +static void mt8183_set_vcore_level(struct mtk_dvfsrc *dvfsrc, u32
> > level)
> > +{
> > +	dvfsrc_write(dvfsrc, DVFSRC_SW_REQ2, level << 2);
> > +}
> > +
> > +void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd,
> > u64 data)
> 
> int mtk_dvfsrc_send_request(......
> 

I would update this on next version

> > +{
> > +	int ret, state;
> > +	struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev);
> > +
> > +	dev_dbg(dvfsrc->dev, "cmd: %d, data: %llu\n", cmd, data);
> > +
> > +	switch (cmd) {
> > +	case MTK_DVFSRC_CMD_BW_REQUEST:
> > +		dvfsrc->dvd->set_dram_bw(dvfsrc, data);
> > +		return;
> > +	case MTK_DVFSRC_CMD_PEAK_BW_REQUEST:
> > +		if (dvfsrc->dvd->set_dram_peak_bw)
> > +			dvfsrc->dvd->set_dram_peak_bw(dvfsrc, data);
> > +		return;
> > +	case MTK_DVFSRC_CMD_OPP_REQUEST:
> > +		if (dvfsrc->dvd->set_opp_level)
> > +			dvfsrc->dvd->set_opp_level(dvfsrc, data);
> > +		break;
> > +	case MTK_DVFSRC_CMD_VCORE_REQUEST:
> > +		dvfsrc->dvd->set_vcore_level(dvfsrc, data);
> > +		break;
> > +	case MTK_DVFSRC_CMD_HRTBW_REQUEST:
> > +		if (dvfsrc->dvd->set_dram_hrtbw)
> > +			dvfsrc->dvd->set_dram_hrtbw(dvfsrc, data);
> > +		else
> > +			return;
> 
> 			return -EINVAL;
> 

I would update this on next version

> > +		break;
> > +	case MTK_DVFSRC_CMD_VSCP_REQUEST:
> > +		dvfsrc->dvd->set_vscp_level(dvfsrc, data);
> > +		break;
> > +	default:
> > +		dev_err(dvfsrc->dev, "unknown command: %d\n", cmd);
> > +		return;
> 
> 		return -EINVAL;
> 

I would update this on next version

> > +	}
> > +
> > +	/* DVFSRC needs to wait at least 2T(~196ns) to handle request
> > +	 * after receiving command
> > +	 */
> > +	udelay(STARTUP_TIME);
> > +
> > +	ret = readx_poll_timeout(dvfsrc_is_idle, dvfsrc,
> > +				 state, state == DVFSRC_IDLE,
> > +				 STARTUP_TIME, POLL_TIMEOUT);
> > +
> > +	if (ret < 0) {
> > +		dev_warn(dvfsrc->dev,
> > +			 "%d: idle timeout, data: %llu, last: %d ->
> > %d\n",
> > +			 cmd, data,
> > +			 dvfsrc->dvd->get_current_level(dvfsrc),
> > +			 dvfsrc->dvd->get_target_level(dvfsrc));
> > +		return;
> 
> 		return ret;
> 

I would update this on next version

> > +	}
> > +
> > +	/* The previous change may be requested by previous request.
> > +	 * So we delay 1us, then start checking opp is reached enough.
> > +	 */
> > +	udelay(STARTUP_TIME);
> > +
> > +	if (cmd == MTK_DVFSRC_CMD_OPP_REQUEST)
> > +		ret = dvfsrc->dvd->wait_for_opp_level(dvfsrc, data);
> > +	else
> > +		ret = dvfsrc->dvd->wait_for_vcore_level(dvfsrc, data);
> > +
> > +	if (ret < 0) {
> > +		dev_warn(dvfsrc->dev,
> > +			 "%d: wait timeout, data: %llu, last: %d ->
> > %d\n",
> > +			 cmd, data,
> > +			 dvfsrc->dvd->get_current_level(dvfsrc),
> > +			 dvfsrc->dvd->get_target_level(dvfsrc));
> > +	}
> > +
> > +}
> > +EXPORT_SYMBOL(mtk_dvfsrc_send_request);
> > +
> > +int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int
> > *data)
> > +{
> > +	struct mtk_dvfsrc *dvfsrc = dev_get_drvdata(dev);
> > +
> > +	switch (cmd) {
> > +	case MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY:
> > +		*data = dvfsrc->dvd->get_vcore_level(dvfsrc);
> > +		break;
> > +	case MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY:
> > +		*data = dvfsrc->dvd->get_vcp_level(dvfsrc);
> > +		break;
> > +	default:
> > +		return -EINVAL;
> > +	}
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL(mtk_dvfsrc_query_info);
> > +
> > +static int mtk_dvfsrc_probe(struct platform_device *pdev)
> > +{
> > +	struct arm_smccc_res ares;
> > +	struct resource *res;
> > +	struct mtk_dvfsrc *dvfsrc;
> > +	int ret;
> > +
> > +	dvfsrc = devm_kzalloc(&pdev->dev, sizeof(*dvfsrc), GFP_KERNEL);
> > +	if (!dvfsrc)
> > +		return -ENOMEM;
> > +
> > +	dvfsrc->dvd = of_device_get_match_data(&pdev->dev);
> > +	dvfsrc->dev = &pdev->dev;
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	dvfsrc->regs = devm_ioremap_resource(&pdev->dev, res);
> > +	if (IS_ERR(dvfsrc->regs))
> > +		return PTR_ERR(dvfsrc->regs);
> > +
> > +	spin_lock_init(&dvfsrc->req_lock);
> > +	mutex_init(&dvfsrc->pstate_lock);
> > +
> > +	arm_smccc_smc(MTK_SIP_VCOREFS_CONTROL, MTK_SIP_DVFSRC_INIT, 0,
> > 0, 0,
> > +		0, 0, 0, &ares);
> > +
> > +	if (!ares.a0) {
> > +		dvfsrc->dram_type = ares.a1;
> > +		dev_info(dvfsrc->dev, "dram_type: %d\n", dvfsrc-
> > >dram_type);
> > +	} else {
> > +		dev_err(dvfsrc->dev, "init fails: %lu\n", ares.a0);
> > +		return ares.a0;
> > +	}
> > +
> > +	dvfsrc->curr_opps = &dvfsrc->dvd->opps_desc[dvfsrc->dram_type];
> > +	platform_set_drvdata(pdev, dvfsrc);
> > +
> > +	dvfsrc->regulator = platform_device_register_data(dvfsrc->dev,
> > +			"mtk-dvfsrc-regulator", -1, NULL, 0);
> 
> Why are you registering platform devices like this?
> 
> Please use device-tree instead.
> 

Thank you for advisement. Let me just describe history.

Actually, we did use device-tree to probe interconnect/regulator driver
in v4, and reviewer had some advisement


https://patchwork.kernel.org/project/linux-mediatek/patch/1584092066-24425-12-git-send-email-henryc.chen@mediatek.com/#23243049

https://patchwork.kernel.org/project/linux-mediatek/patch/1584092066-24425-9-git-send-email-henryc.chen@mediatek.com/#23236945

so we refer to this driver to use platform_device_register_data after
v5.

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/soc/qcom/smd-rpm.c?h=next-20220209#n213

Would you kindly give your advisement, thank you.

> > +	if (IS_ERR(dvfsrc->regulator)) {
> > +		dev_err(dvfsrc->dev, "Failed create regulator
> > device\n");
> > +		ret = PTR_ERR(dvfsrc->regulator);
> > +		goto err;
> > +	}
> > +
> > +	dvfsrc->icc = platform_device_register_data(dvfsrc->dev,
> > +			"mediatek-emi-icc", -1, NULL, 0);
> 
> Same here.
> 
> > +	if (IS_ERR(dvfsrc->icc)) {
> > +		dev_err(dvfsrc->dev, "Failed create icc device\n");
> 
> As a side note, after applying the suggested flow, you will also be
> able
> to use dev_err_probe() instead, simplifying this probe function.
> 

I would update this on next version

> > +		ret = PTR_ERR(dvfsrc->icc);
> > +		goto unregister_regulator;
> > +	}
> > +
> > +	ret = devm_of_platform_populate(&pdev->dev);
> > +	if (ret)
> > +		platform_device_unregister(dvfsrc->icc);
> > +
> > +	return 0;
> > +
> > +unregister_regulator:
> > +	platform_device_unregister(dvfsrc->regulator);
> > +err:
> > +	return ret;
> > +}
> > +
> > +static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp4[] = {
> > +	{0, 0}, {0, 1}, {0, 2}, {1, 2},
> > +};
> > +
> > +static const struct dvfsrc_opp dvfsrc_opp_mt8183_lp3[] = {
> > +	{0, 0}, {0, 1}, {1, 1}, {1, 2},
> > +};
> > +
> > +static const struct dvfsrc_opp_desc dvfsrc_opp_mt8183_desc[] = {
> > +	DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp4),
> > +	DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp3),
> > +	DVFSRC_OPP_DESC(dvfsrc_opp_mt8183_lp3),
> > +};
> > +
> > +static const struct dvfsrc_soc_data mt8183_data = {
> > +	.opps_desc = dvfsrc_opp_mt8183_desc,
> > +	.regs = mt8183_regs,
> > +	.get_target_level = mt8183_get_target_level,
> > +	.get_current_level = mt8183_get_current_level,
> > +	.get_vcore_level = mt8183_get_vcore_level,
> > +	.set_dram_bw = mt8183_set_dram_bw,
> > +	.set_opp_level = mt8183_set_opp_level,
> > +	.set_vcore_level = mt8183_set_vcore_level,
> > +	.wait_for_opp_level = mt8183_wait_for_opp_level,
> > +	.wait_for_vcore_level = dvfsrc_wait_for_vcore_level,
> > +};
> > +
> > +static int mtk_dvfsrc_remove(struct platform_device *pdev)
> > +{
> > +	struct mtk_dvfsrc *dvfsrc = platform_get_drvdata(pdev);
> > +
> > +	platform_device_unregister(dvfsrc->regulator);
> > +	platform_device_unregister(dvfsrc->icc);
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_dvfsrc_of_match[] = {
> > +	{
> > +		.compatible = "mediatek,mt8183-dvfsrc",
> > +		.data = &mt8183_data,
> > +	}, {
> > +		/* sentinel */
> > +	},
> > +};
> > +
> > +static struct platform_driver mtk_dvfsrc_driver = {
> > +	.probe	= mtk_dvfsrc_probe,
> > +	.remove	= mtk_dvfsrc_remove,
> > +	.driver = {
> > +		.name = "mtk-dvfsrc",
> > +		.of_match_table = of_match_ptr(mtk_dvfsrc_of_match),
> > +	},
> > +};
> > +
> > +static int __init mtk_dvfsrc_init(void)
> > +{
> > +	return platform_driver_register(&mtk_dvfsrc_driver);
> > +}
> > +subsys_initcall(mtk_dvfsrc_init);
> > +
> > +static void __exit mtk_dvfsrc_exit(void)
> > +{
> > +	platform_driver_unregister(&mtk_dvfsrc_driver);
> > +}
> > +module_exit(mtk_dvfsrc_exit);
> > +
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_DESCRIPTION("MTK DVFSRC driver");
> > diff --git a/include/linux/soc/mediatek/mtk_dvfsrc.h
> > b/include/linux/soc/mediatek/mtk_dvfsrc.h
> > new file mode 100644
> > index 000000000000..823eff9bb19f
> > --- /dev/null
> > +++ b/include/linux/soc/mediatek/mtk_dvfsrc.h
> > @@ -0,0 +1,35 @@
> > +/* SPDX-License-Identifier: GPL-2.0
> > + *
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#ifndef __SOC_MTK_DVFSRC_H
> > +#define __SOC_MTK_DVFSRC_H
> > +
> > +#define MTK_DVFSRC_CMD_BW_REQUEST		0
> > +#define MTK_DVFSRC_CMD_OPP_REQUEST		1
> > +#define MTK_DVFSRC_CMD_VCORE_REQUEST		2
> > +#define MTK_DVFSRC_CMD_HRTBW_REQUEST		3
> > +#define MTK_DVFSRC_CMD_VSCP_REQUEST		4
> > +#define MTK_DVFSRC_CMD_PEAK_BW_REQUEST		5
> > +
> > +#define MTK_DVFSRC_CMD_VCORE_LEVEL_QUERY	0
> > +#define MTK_DVFSRC_CMD_VSCP_LEVEL_QUERY		1
> > +
> > +#if IS_ENABLED(CONFIG_MTK_DVFSRC)
> > +void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd,
> > u64 data);
> > +int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int
> > *data);
> > +
> > +#else
> > +
> > +static inline void mtk_dvfsrc_send_request(const struct device
> > *dev, u32 cmd,
> > +					   u64 data)
> > +{ return -ENODEV; }
> > +
> > +static inline int mtk_dvfsrc_query_info(const struct device *dev,
> > u32 cmd,
> > +					int *data);
> > +{ return -ENODEV; }
> > +
> > +#endif /* CONFIG_MTK_DVFSRC */
> > +
> > +#endif


^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [V11,PATCH 04/19] soc: mediatek: add driver for dvfsrc support
  2022-02-11  3:51     ` Dawei Chien
@ 2022-02-11 11:50       ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 36+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-02-11 11:50 UTC (permalink / raw)
  To: Dawei Chien, Georgi Djakov, Rob Herring, Matthias Brugger,
	Stephen Boyd, Ryan Case
  Cc: Mark Rutland, Nicolas Boichat, devicetree, linux-pm,
	linux-kernel, linux-mediatek, linux-arm-kernel, Fan Chen,
	Arvin Wang, James Liao, Henry Chen

Il 11/02/22 04:51, Dawei Chien ha scritto:
> On Thu, 2022-02-03 at 16:04 +0100, AngeloGioacchino Del Regno wrote:
>> Il 12/08/21 10:58, Dawei Chien ha scritto:
>>> From: Henry Chen <henryc.chen@mediatek.com>
>>>
>>> Add dvfsrc driver for MT6873/MT8183/MT8192
>>>
>>> Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
>>> Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
>>> ---
>>>    drivers/soc/mediatek/Kconfig            |  11 +
>>>    drivers/soc/mediatek/Makefile           |   1 +
>>>    drivers/soc/mediatek/mtk-dvfsrc.c       | 421
>>> ++++++++++++++++++++++++++++++++
>>>    include/linux/soc/mediatek/mtk_dvfsrc.h |  35 +++
>>>    4 files changed, 468 insertions(+)
>>>    create mode 100644 drivers/soc/mediatek/mtk-dvfsrc.c
>>>    create mode 100644 include/linux/soc/mediatek/mtk_dvfsrc.h
>>>

..snip..

>>> diff --git a/drivers/soc/mediatek/mtk-dvfsrc.c
>>> b/drivers/soc/mediatek/mtk-dvfsrc.c
>>> new file mode 100644
>>> index 000000000000..6ef167cf55bd
>>> --- /dev/null
>>> +++ b/drivers/soc/mediatek/mtk-dvfsrc.c

..snip..

>>> +static int mtk_dvfsrc_probe(struct platform_device *pdev)
>>> +{
>>> +	struct arm_smccc_res ares;
>>> +	struct resource *res;
>>> +	struct mtk_dvfsrc *dvfsrc;
>>> +	int ret;
>>> +
>>> +	dvfsrc = devm_kzalloc(&pdev->dev, sizeof(*dvfsrc), GFP_KERNEL);
>>> +	if (!dvfsrc)
>>> +		return -ENOMEM;
>>> +
>>> +	dvfsrc->dvd = of_device_get_match_data(&pdev->dev);
>>> +	dvfsrc->dev = &pdev->dev;
>>> +
>>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +	dvfsrc->regs = devm_ioremap_resource(&pdev->dev, res);
>>> +	if (IS_ERR(dvfsrc->regs))
>>> +		return PTR_ERR(dvfsrc->regs);
>>> +
>>> +	spin_lock_init(&dvfsrc->req_lock);
>>> +	mutex_init(&dvfsrc->pstate_lock);
>>> +
>>> +	arm_smccc_smc(MTK_SIP_VCOREFS_CONTROL, MTK_SIP_DVFSRC_INIT, 0,
>>> 0, 0,
>>> +		0, 0, 0, &ares);
>>> +
>>> +	if (!ares.a0) {
>>> +		dvfsrc->dram_type = ares.a1;
>>> +		dev_info(dvfsrc->dev, "dram_type: %d\n", dvfsrc-
>>>> dram_type);
>>> +	} else {
>>> +		dev_err(dvfsrc->dev, "init fails: %lu\n", ares.a0);
>>> +		return ares.a0;
>>> +	}
>>> +
>>> +	dvfsrc->curr_opps = &dvfsrc->dvd->opps_desc[dvfsrc->dram_type];
>>> +	platform_set_drvdata(pdev, dvfsrc);
>>> +
>>> +	dvfsrc->regulator = platform_device_register_data(dvfsrc->dev,
>>> +			"mtk-dvfsrc-regulator", -1, NULL, 0);
>>
>> Why are you registering platform devices like this?
>>
>> Please use device-tree instead.
>>
> 
> Thank you for advisement. Let me just describe history.
> 
> Actually, we did use device-tree to probe interconnect/regulator driver
> in v4, and reviewer had some advisement
> 
> 
> https://patchwork.kernel.org/project/linux-mediatek/patch/1584092066-24425-12-git-send-email-henryc.chen@mediatek.com/#23243049
> 
> https://patchwork.kernel.org/project/linux-mediatek/patch/1584092066-24425-9-git-send-email-henryc.chen@mediatek.com/#23236945
> 
> so we refer to this driver to use platform_device_register_data after
> v5.
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/soc/qcom/smd-rpm.c?h=next-20220209#n213
> 
> Would you kindly give your advisement, thank you.
> 

Hello Dawei,
I was under the impression that the regulator and EMI were different hardware,
while effectively they are inside of the DVFS Resource Collector IP, and the
registers look like being a bit mixed up, so it's impossible to actually
specify a relative iospace for the regulator, or for the EMI.

In this case, from what I understand right now, the emi and regulator are not
different hardware, but "features of" the DVFS Resource Collector.

I've done some research around the kernel and, effectively, the only way that
makes sense, is to register the feature-drivers (emi/vreg) with
platform_device_register_data(), as per your current approach, even though I
have a hunch that it will look a bit confusing in device-tree, as you'd be using
the same node for both regulator and interconnects...

I would exclude doing it as a MFD driver, as I don't see any very clean way to
actually implement that.

At this point, let's just keep it as it is, or this would probably get a lot
overcomplicated for no good reasons.
So, please ignore the device-tree suggestion and go on with the other suggested
fixes for this driver.

Looking forward to see your v4!

Kind regards,
Angelo

^ permalink raw reply	[flat|nested] 36+ messages in thread

end of thread, other threads:[~2022-02-11 11:50 UTC | newest]

Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-12  8:58 [PATCH 00/19] Add driver for dvfsrc, support for interconnect Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 01/19] dt-bindings: soc: Add dvfsrc driver bindings Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 02/19] dt-bindings: mediatek: add compatible for MT8195 dvfsrc Dawei Chien
2021-08-17 21:23   ` Rob Herring
2021-08-12  8:58 ` [V11,PATCH 03/19] soc: mediatek: add header for mediatek SIP interface Dawei Chien
2022-02-03 15:14   ` [V11, PATCH " AngeloGioacchino Del Regno
2022-02-11  3:50     ` Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 04/19] soc: mediatek: add driver for dvfsrc support Dawei Chien
2022-02-03 15:04   ` AngeloGioacchino Del Regno
2022-02-11  3:51     ` Dawei Chien
2022-02-11 11:50       ` AngeloGioacchino Del Regno
2021-08-12  8:58 ` [V11,PATCH 05/19] soc: mediatek: add support for mt6873 Dawei Chien
2022-02-03 15:13   ` AngeloGioacchino Del Regno
2022-02-11  3:50     ` Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 06/19] soc: mediatek: add support for mt8195 Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 07/19] arm64: dts: mt8183: add dvfsrc related nodes Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 08/19] arm64: dts: mt8192: " Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 09/19] arm64: dts: mt8195: " Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 10/19] dt-bindings: interconnect: add MT6873 interconnect dt-bindings Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 11/19] dt-bindings: interconnect: add MT8195 " Dawei Chien
2021-08-17 21:24   ` Rob Herring
2022-02-03 15:22   ` [V11, PATCH " AngeloGioacchino Del Regno
2021-08-12  8:58 ` [V11,PATCH 12/19] interconnect: mediatek: Add interconnect provider driver Dawei Chien
2022-02-03 15:19   ` [V11, PATCH " AngeloGioacchino Del Regno
2022-02-11  3:49     ` Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 13/19] interconnect: mediatek: add support for mt8195 Dawei Chien
2022-02-03 15:19   ` AngeloGioacchino Del Regno
2021-08-12  8:58 ` [V11,PATCH 14/19] interconnect: mediatek: add initial bandwidth Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 15/19] regulator: mediatek: add support for mt8195 Dawei Chien
2022-02-03 15:21   ` AngeloGioacchino Del Regno
2021-08-12  8:58 ` [V11,PATCH 16/19] arm64: dts: mt8183: add dvfsrc related nodes Dawei Chien
2022-02-03 15:16   ` AngeloGioacchino Del Regno
2022-02-11  3:50     ` Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 17/19] arm64: dts: mt8192: " Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 18/19] arm64: dts: mt8192: add dvfsrc regulator nodes Dawei Chien
2021-08-12  8:58 ` [V11,PATCH 19/19] arm64: dts: mt8195: add dvfsrc related nodes Dawei Chien

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