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From: Daniel Vetter <daniel@ffwll.ch>
To: Rob Clark <robdclark@gmail.com>
Cc: dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"Christian König" <ckoenig.leichtzumerken@gmail.com>,
	"Michel Dänzer" <michel@daenzer.net>,
	"Pekka Paalanen" <ppaalanen@gmail.com>,
	"Rob Clark" <robdclark@chromium.org>,
	"Sean Paul" <sean@poorly.run>, "David Airlie" <airlied@linux.ie>,
	"Sumit Semwal" <sumit.semwal@linaro.org>,
	"Christian König" <christian.koenig@amd.com>,
	"open list:DRM DRIVER FOR MSM ADRENO GPU"
	<linux-arm-msm@vger.kernel.org>,
	"open list:DRM DRIVER FOR MSM ADRENO GPU"
	<freedreno@lists.freedesktop.org>,
	"open list" <linux-kernel@vger.kernel.org>,
	"open list:DMA BUFFER SHARING FRAMEWORK"
	<linux-media@vger.kernel.org>
Subject: Re: [PATCH v3 5/9] drm/msm: Add deadline based boost support
Date: Wed, 8 Sep 2021 19:48:26 +0200	[thread overview]
Message-ID: <YTj3akinO0jVbCFc@phenom.ffwll.local> (raw)
In-Reply-To: <20210903184806.1680887-6-robdclark@gmail.com>

On Fri, Sep 03, 2021 at 11:47:56AM -0700, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
> 
> Signed-off-by: Rob Clark <robdclark@chromium.org>

Why do you need a kthread_work here? Is this just to make sure you're
running at realtime prio? Maybe a comment to that effect would be good.
-Daniel

> ---
>  drivers/gpu/drm/msm/msm_fence.c       | 76 +++++++++++++++++++++++++++
>  drivers/gpu/drm/msm/msm_fence.h       | 20 +++++++
>  drivers/gpu/drm/msm/msm_gpu.h         |  1 +
>  drivers/gpu/drm/msm/msm_gpu_devfreq.c | 20 +++++++
>  4 files changed, 117 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c
> index f2cece542c3f..67c2a96e1c85 100644
> --- a/drivers/gpu/drm/msm/msm_fence.c
> +++ b/drivers/gpu/drm/msm/msm_fence.c
> @@ -8,6 +8,37 @@
>  
>  #include "msm_drv.h"
>  #include "msm_fence.h"
> +#include "msm_gpu.h"
> +
> +static inline bool fence_completed(struct msm_fence_context *fctx, uint32_t fence);
> +
> +static struct msm_gpu *fctx2gpu(struct msm_fence_context *fctx)
> +{
> +	struct msm_drm_private *priv = fctx->dev->dev_private;
> +	return priv->gpu;
> +}
> +
> +static enum hrtimer_restart deadline_timer(struct hrtimer *t)
> +{
> +	struct msm_fence_context *fctx = container_of(t,
> +			struct msm_fence_context, deadline_timer);
> +
> +	kthread_queue_work(fctx2gpu(fctx)->worker, &fctx->deadline_work);
> +
> +	return HRTIMER_NORESTART;
> +}
> +
> +static void deadline_work(struct kthread_work *work)
> +{
> +	struct msm_fence_context *fctx = container_of(work,
> +			struct msm_fence_context, deadline_work);
> +
> +	/* If deadline fence has already passed, nothing to do: */
> +	if (fence_completed(fctx, fctx->next_deadline_fence))
> +		return;
> +
> +	msm_devfreq_boost(fctx2gpu(fctx), 2);
> +}
>  
>  
>  struct msm_fence_context *
> @@ -26,6 +57,13 @@ msm_fence_context_alloc(struct drm_device *dev, volatile uint32_t *fenceptr,
>  	fctx->fenceptr = fenceptr;
>  	spin_lock_init(&fctx->spinlock);
>  
> +	hrtimer_init(&fctx->deadline_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
> +	fctx->deadline_timer.function = deadline_timer;
> +
> +	kthread_init_work(&fctx->deadline_work, deadline_work);
> +
> +	fctx->next_deadline = ktime_get();
> +
>  	return fctx;
>  }
>  
> @@ -49,6 +87,8 @@ void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence)
>  {
>  	spin_lock(&fctx->spinlock);
>  	fctx->completed_fence = max(fence, fctx->completed_fence);
> +	if (fence_completed(fctx, fctx->next_deadline_fence))
> +		hrtimer_cancel(&fctx->deadline_timer);
>  	spin_unlock(&fctx->spinlock);
>  }
>  
> @@ -79,10 +119,46 @@ static bool msm_fence_signaled(struct dma_fence *fence)
>  	return fence_completed(f->fctx, f->base.seqno);
>  }
>  
> +static void msm_fence_set_deadline(struct dma_fence *fence, ktime_t deadline)
> +{
> +	struct msm_fence *f = to_msm_fence(fence);
> +	struct msm_fence_context *fctx = f->fctx;
> +	unsigned long flags;
> +	ktime_t now;
> +
> +	spin_lock_irqsave(&fctx->spinlock, flags);
> +	now = ktime_get();
> +
> +	if (ktime_after(now, fctx->next_deadline) ||
> +			ktime_before(deadline, fctx->next_deadline)) {
> +		fctx->next_deadline = deadline;
> +		fctx->next_deadline_fence =
> +			max(fctx->next_deadline_fence, (uint32_t)fence->seqno);
> +
> +		/*
> +		 * Set timer to trigger boost 3ms before deadline, or
> +		 * if we are already less than 3ms before the deadline
> +		 * schedule boost work immediately.
> +		 */
> +		deadline = ktime_sub(deadline, ms_to_ktime(3));
> +
> +		if (ktime_after(now, deadline)) {
> +			kthread_queue_work(fctx2gpu(fctx)->worker,
> +					&fctx->deadline_work);
> +		} else {
> +			hrtimer_start(&fctx->deadline_timer, deadline,
> +					HRTIMER_MODE_ABS);
> +		}
> +	}
> +
> +	spin_unlock_irqrestore(&fctx->spinlock, flags);
> +}
> +
>  static const struct dma_fence_ops msm_fence_ops = {
>  	.get_driver_name = msm_fence_get_driver_name,
>  	.get_timeline_name = msm_fence_get_timeline_name,
>  	.signaled = msm_fence_signaled,
> +	.set_deadline = msm_fence_set_deadline,
>  };
>  
>  struct dma_fence *
> diff --git a/drivers/gpu/drm/msm/msm_fence.h b/drivers/gpu/drm/msm/msm_fence.h
> index 4783db528bcc..d34e853c555a 100644
> --- a/drivers/gpu/drm/msm/msm_fence.h
> +++ b/drivers/gpu/drm/msm/msm_fence.h
> @@ -50,6 +50,26 @@ struct msm_fence_context {
>  	volatile uint32_t *fenceptr;
>  
>  	spinlock_t spinlock;
> +
> +	/*
> +	 * TODO this doesn't really deal with multiple deadlines, like
> +	 * if userspace got multiple frames ahead.. OTOH atomic updates
> +	 * don't queue, so maybe that is ok
> +	 */
> +
> +	/** next_deadline: Time of next deadline */
> +	ktime_t next_deadline;
> +
> +	/**
> +	 * next_deadline_fence:
> +	 *
> +	 * Fence value for next pending deadline.  The deadline timer is
> +	 * canceled when this fence is signaled.
> +	 */
> +	uint32_t next_deadline_fence;
> +
> +	struct hrtimer deadline_timer;
> +	struct kthread_work deadline_work;
>  };
>  
>  struct msm_fence_context * msm_fence_context_alloc(struct drm_device *dev,
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> index 0e4b45bff2e6..e031c9b495ed 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
> @@ -425,6 +425,7 @@ void msm_devfreq_init(struct msm_gpu *gpu);
>  void msm_devfreq_cleanup(struct msm_gpu *gpu);
>  void msm_devfreq_resume(struct msm_gpu *gpu);
>  void msm_devfreq_suspend(struct msm_gpu *gpu);
> +void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
>  void msm_devfreq_active(struct msm_gpu *gpu);
>  void msm_devfreq_idle(struct msm_gpu *gpu);
>  
> diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
> index 0a1ee20296a2..8a8d7b9028a3 100644
> --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c
> +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
> @@ -144,6 +144,26 @@ void msm_devfreq_suspend(struct msm_gpu *gpu)
>  	devfreq_suspend_device(gpu->devfreq.devfreq);
>  }
>  
> +void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor)
> +{
> +	struct msm_gpu_devfreq *df = &gpu->devfreq;
> +	unsigned long freq;
> +
> +	/*
> +	 * Hold devfreq lock to synchronize with get_dev_status()/
> +	 * target() callbacks
> +	 */
> +	mutex_lock(&df->devfreq->lock);
> +
> +	freq = get_freq(gpu);
> +
> +	freq *= factor;
> +
> +	msm_devfreq_target(&gpu->pdev->dev, &freq, 0);
> +
> +	mutex_unlock(&df->devfreq->lock);
> +}
> +
>  void msm_devfreq_active(struct msm_gpu *gpu)
>  {
>  	struct msm_gpu_devfreq *df = &gpu->devfreq;
> -- 
> 2.31.1
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

  reply	other threads:[~2021-09-08 17:48 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-03 18:47 [PATCH v3 0/9] dma-fence: Deadline awareness Rob Clark
2021-09-03 18:47 ` [PATCH v3 1/9] dma-fence: Add deadline awareness Rob Clark
2021-09-08 17:55   ` Daniel Vetter
2021-09-03 18:47 ` [PATCH v3 2/9] drm/vblank: Add helper to get next vblank time Rob Clark
2021-09-03 18:47 ` [PATCH v3 3/9] drm/atomic-helper: Set fence deadline for vblank Rob Clark
2021-09-03 18:47 ` [PATCH v3 4/9] drm/scheduler: Add fence deadline support Rob Clark
2021-09-08 17:45   ` Daniel Vetter
2021-09-09  6:22     ` Christian König
2021-09-14 13:38       ` Daniel Vetter
2021-09-21 15:57     ` Rob Clark
2021-09-21 16:35       ` Rob Clark
2021-09-21 16:45         ` Christian König
2021-09-21 20:09   ` Andrey Grodzovsky
2021-09-21 20:47     ` Rob Clark
2021-09-22  2:18       ` Andrey Grodzovsky
2021-09-22  3:32         ` Rob Clark
2021-09-22 14:31           ` Andrey Grodzovsky
2021-09-22 15:01             ` Rob Clark
2021-09-03 18:47 ` [PATCH v3 5/9] drm/msm: Add deadline based boost support Rob Clark
2021-09-08 17:48   ` Daniel Vetter [this message]
2021-09-08 17:57     ` Rob Clark
2021-09-03 18:47 ` [PATCH v3 6/9] dma-buf/fence-array: Add fence deadline support Rob Clark
2021-09-08 18:00   ` Daniel Vetter
2021-09-09  6:55     ` Christian König
2021-09-03 18:47 ` [PATCH v3 7/9] dma-buf/fence-chain: " Rob Clark
2021-09-08 17:54   ` Daniel Vetter
2021-09-08 18:19     ` Rob Clark
2021-09-08 18:45       ` Daniel Vetter
2021-09-09  6:31         ` Christian König
2021-09-03 18:47 ` [PATCH v3 8/9] dma-buf/sync_file: Add SET_DEADLINE ioctl Rob Clark
2021-09-08 17:50   ` Daniel Vetter
2021-09-08 18:23     ` Rob Clark
2021-09-08 18:49       ` Daniel Vetter
2021-09-08 19:40         ` Rob Clark
2021-09-08 21:10           ` Daniel Vetter
2021-09-21 18:08             ` Rob Clark
2021-09-27  8:42   ` Pekka Paalanen
2021-09-27  8:53     ` Christian König
2021-09-27 14:36     ` Rob Clark
2021-09-28  7:57       ` Pekka Paalanen
2021-09-03 18:48 ` [PATCH v3 9/9] dma-buf/sw_sync: Add fence deadline support Rob Clark
2021-09-09 16:16 ` [PATCH v3 0/9] dma-fence: Deadline awareness Simon Ser
2021-09-09 16:35   ` Rob Clark
2021-09-09 16:42     ` Simon Ser
2021-09-09 17:08       ` Rob Clark

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