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([2001:b07:6468:f312:63a7:c72e:ea0e:6045]) by smtp.gmail.com with ESMTPSA id r20sm1522212ejz.120.2021.08.19.09.36.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Aug 2021 09:36:14 -0700 (PDT) Subject: Re: [PATCH v3 2/3] KVM: x86: Handle the case of 5-level shadow page table To: Sean Christopherson , Wei Huang Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com, joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, x86@kernel.org, hpa@zytor.com References: <20210818165549.3771014-1-wei.huang2@amd.com> <20210818165549.3771014-3-wei.huang2@amd.com> From: Paolo Bonzini Message-ID: Date: Thu, 19 Aug 2021 18:36:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18/08/21 19:15, Sean Christopherson wrote: >> When the 5-level page table CPU flag is exposed, KVM code needs to handle >> this case by pointing mmu->root_hpa to a properly-constructed 5-level page >> table. > Similarly, this is wrong, or maybe just poorly worded. This has nothing to do > with LA57 being exposed to the guest, it's purely the host using 5-level paging > and NPT being enabled and exposed to L1. Like this: --- KVM: x86/mmu: Support shadowing NPT when 5-level paging is enabled in host When the 5-level page table CPU flag is set in the host, but the guest has CR4.LA57=0 (including the case of a 32-bit guest), the top level of the shadow NPT page tables will be fixed, consisting of one pointer to a lower-level table and 511 non-present entries. Extend the existing code that creates the fixed PML4 or PDP table, to provide a fixed PML5 table if needed. This is not needed on EPT because the number of layers in the tables is specified in the EPTP instead of depending on the host CR4. --- Paolo