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From: Richard Laing <Richard.Laing@alliedtelesis.co.nz>
To: Loic Poulain <loic.poulain@linaro.org>
Cc: David Miller <davem@davemloft.net>,
	Network Development <netdev@vger.kernel.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] bus: mhi: pci-generic: configurable network interface MRU
Date: Tue, 27 Jul 2021 20:49:52 +0000	[thread overview]
Message-ID: <a984248c-c9be-b8e0-b6bc-1cf2aabb09f5@alliedtelesis.co.nz> (raw)
In-Reply-To: <CAMZdPi8MZp5Vx_ZnjjQWptms9vj6bEMoV83pcv4wmgxbZz0wjQ@mail.gmail.com>



On 7/27/21 9:21 PM, Loic Poulain wrote:
> Note that the default MRU you define is not MHI controller specific
> but MHI channel specific (IP/MBIM channel), so it should not be a
> property of the MHI controller. AFAIK, The MHI specification already
> defines MRU for the transfered buffers which is 65535. I would
> recommend to move this prop to the channel config.

That makes sense thank you. I assume the UL and DL channels could be 
expected to have the same MRU?

Regards,
Richard

      reply	other threads:[~2021-07-27 20:49 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-14 21:18 richard.laing
2021-07-15 17:20 ` patchwork-bot+netdevbpf
2021-07-19 10:11 ` Loic Poulain
2021-07-19 21:44   ` Richard Laing
2021-07-27  9:21     ` Loic Poulain
2021-07-27 20:49       ` Richard Laing [this message]

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