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From: Thomas Gleixner <tglx@linutronix.de>
To: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Cc: "mingo@redhat.com" <mingo@redhat.com>,
	"hpa@zytor.com" <hpa@zytor.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"rjw@rjwysocki.net" <rjw@rjwysocki.net>,
	"lenb@kernel.org" <lenb@kernel.org>,
	David Wang <DavidWang@zhaoxin.com>,
	"Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>,
	"Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>,
	"Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Subject: Re: [PATCH v2 0/3] Add support for Zhaoxin Processors
Date: Fri, 14 Jun 2019 17:06:57 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.21.1906141705400.1722@nanos.tec.linutronix.de> (raw)
In-Reply-To: <54fb8565afbe4351adc0e4541463776c@zhaoxin.com>

Tony,

On Tue, 28 May 2019, Tony W Wang-oc wrote:

> As a new x86 CPU Vendor, Shanghai Zhaoxin Semiconductor Co., Ltd.
>  ("Zhaoxin") provide high performance general-purpose x86 processors.
> 
> CPU Vendor ID "Shanghai" belongs to Zhaoxin.
> 
> To enable the supports of Linux kernel to Zhaoxin's CPUs, add a new vendor
> type (X86_VENDOR_ZHAOXIN, with value of 10) in
> arch/x86/include/asm/processor.h.
> 
> To enable the support of Linux kernel's specific configuration to
> Zhaoxin's CPUs, add a new file arch/x86/kernel/cpu/zhaoxin.c.
> 
> This patch series have been applied and tested successfully on Zhaoxin's
> Soc silicon. Also tested on other processors, it works fine and makes no
> harm to the existing codes.
> 
> v1->v2:
>  - Rebased on 5.2.0-rc2 and tested against it.
>  - remove GPL "boilerplate" text in the patch.
>  - adjust signed-off-by: line match From: line.
>  - run patch series through checkpatch.pl.
> 
> v1:
>  - Rebased on 5.2.0-rc1 and tested against it.
>  - Split the patch set to small series of patches.
>  - Rework patch descriptions.
> 
> TonyWWang (3):
>  x86/cpu: Create Zhaoxin processors architecture support file
>  ACPI, x86: add Zhaoxin processors support for NONSTOP TSC
>  x86/acpi/cstate: add Zhaoxin processors support for cache flush policy
>  in C3

I only got 0/3 and 1/3 of Version 2. Please always send the complete set.

Thanks,

	tglx

  reply	other threads:[~2019-06-14 15:07 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-28 11:30 Tony W Wang-oc
2019-06-14 15:06 ` Thomas Gleixner [this message]
2019-06-18  8:36 Tony W Wang-oc

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