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From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Nikolai Zhubr <zhubr.2@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Len Brown <len.brown@intel.com>, Pavel Machek <pavel@ucw.cz>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
x86@kernel.org, linux-pci@vger.kernel.org,
linux-pm@vger.kernel.org, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/6] x86: PIRQ/ELCR-related fixes and updates
Date: Tue, 17 Aug 2021 00:30:39 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.21.2108160027350.45958@angie.orcam.me.uk> (raw)
In-Reply-To: <611993B1.4070302@gmail.com>
Hi Nikolai,
> > Nikolai: for your system only 1/6 and 2/6 are required, though you are
> > free to experiment with all the patches. Mind that 3/6 mechanically
> > depends on the earlier change for the SIO PIRQ router referred above. In
> > any case please use the debug patch for PCI code as well as the earlier
> > patches for your other system and send the resulting bootstrap log for
> > confirmation.
>
> Here is a new log with 1/6 and 2/6 applied:
>
> https://pastebin.com/0MgXAGtG
>
> It looks like something went a bit unexpected ("runtime IRQ mapping not
> provided by arch").
Offhand it looks like your system does not supply a PIRQ table, not at
least at the usual locations we look through. The presence of the table
is reported like:
PCI: IRQ init
PCI: Interrupt Routing Table found at 0xfde10
[...]
PCI: IRQ fixup
while your system says:
PCI: IRQ init
PCI: IRQ fixup
If you have a look through /dev/mem and see if there's a "$PIR" signature
somewhere (though not a Linux kernel area of course), then we may know for
sure.
I'm a little busy at the moment with other stuff and may not be able to
look into it properly right now. There may be no solution, not at least
an easy one. A DMI quirk is not possible, because:
DMI not present or invalid.
There is a PCI BIOS:
PCI: PCI BIOS revision 2.10 entry at 0xf6f41, last bus=0
however, so CONFIG_PCI_BIOS just might work. Please try that too, by
choosing CONFIG_PCI_GOANY or CONFIG_PCI_GOBIOS (it may break things
horribly though I imagine).
Maciej
prev parent reply other threads:[~2021-08-16 22:30 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-20 3:27 Maciej W. Rozycki
2021-07-20 3:27 ` [PATCH 1/6] x86: Add support for 0x22/0x23 port I/O configuration space Maciej W. Rozycki
2021-08-10 21:35 ` [tip: x86/irq] " tip-bot2 for Maciej W. Rozycki
2021-07-20 3:27 ` [PATCH 2/6] x86/PCI: Add support for the ALi M1487 (IBC) PIRQ router Maciej W. Rozycki
2021-08-10 21:35 ` [tip: x86/irq] " tip-bot2 for Maciej W. Rozycki
2021-07-20 3:27 ` [PATCH 3/6] x86/PCI: Add support for the Intel 82374EB/82374SB (ESC) " Maciej W. Rozycki
2021-08-10 21:35 ` [tip: x86/irq] " tip-bot2 for Maciej W. Rozycki
2021-07-20 3:28 ` [PATCH 4/6] x86/PCI: Add support for the Intel 82426EX " Maciej W. Rozycki
2021-08-10 21:35 ` [tip: x86/irq] " tip-bot2 for Maciej W. Rozycki
2021-07-20 3:28 ` [PATCH 5/6] x86: Avoid magic number with ELCR register accesses Maciej W. Rozycki
2021-08-10 21:35 ` [tip: x86/irq] " tip-bot2 for Maciej W. Rozycki
2021-07-20 3:28 ` [PATCH 6/6] x86: Fix typo s/ECLR/ELCR/ for the PIC register Maciej W. Rozycki
2021-08-10 21:35 ` [tip: x86/irq] " tip-bot2 for Maciej W. Rozycki
2021-07-21 0:12 ` [PATCH 0/6] x86: PIRQ/ELCR-related fixes and updates Bjorn Helgaas
2021-07-21 20:41 ` Thomas Gleixner
2021-08-15 22:22 ` Nikolai Zhubr
2021-08-16 22:30 ` Maciej W. Rozycki [this message]
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