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From: "Vaden, Tom (HPE Server OS Architecture)" <tom.vaden@hpe.com>
To: Jiri Olsa <jolsa@redhat.com>,
	"Liang, Kan" <kan.liang@linux.intel.com>,
	Peter Zijlstra <peterz@infradead.org>
Cc: Jiri Olsa <jolsa@kernel.org>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	lkml <linux-kernel@vger.kernel.org>,
	Ingo Molnar <mingo@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH] perf/x86/intel: Disable check_msr for real hw
Date: Sun, 16 Jun 2019 20:56:19 +0000	[thread overview]
Message-ID: <b084a989-a39c-0da4-6b68-9e3094b2344e@hpe.com> (raw)
In-Reply-To: <20190616141313.GD2500@krava>



On 6/16/19 10:13 AM, Jiri Olsa wrote:
> On Fri, Jun 14, 2019 at 09:45:21AM -0400, Liang, Kan wrote:
>>
>>
>> On 6/14/2019 7:28 AM, Jiri Olsa wrote:
>>> hi,
>>> the HPE server can do POST tracing and have enabled LBR
>>> tracing during the boot, which makes check_msr fail falsly.
>>>
>>> It looks like check_msr code was added only to check on guests
>>> MSR access, would it be then ok to disable check_msr for real
>>> hardware? (as in patch below)
>>
>> Yes, the check_msr patch was to fix a bug report in guest.
>> I didn't get similar bug report for real hardware.
>> I think it should be OK to disable it for real hardware.
>>
> 
> thanks for confirmation, attaching the full patch
> 
> thanks,
> jirka
> 
> 
> ---
> Tom Vaden reported false failure of check_msr function, because
> some servers can do POST tracing and enable LBR tracing during
> the boot.
> 
> Kan confirmed that check_msr patch was to fix a bug report in
> guest, so it's ok to disable it for real HW.
> 
> Cc: Kan Liang <kan.liang@intel.com>
> Reported-by: Tom Vaden <tom.vaden@hpe.com>
> Signed-off-by: Jiri Olsa <jolsa@kernel.org>

Thanks for handling the patch.

Acked-by: Tom Vaden <tom.vaden@hpe.com>

> ---
>   arch/x86/events/intel/core.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 71001f005bfe..1194ae7e1992 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -20,6 +20,7 @@
>   #include <asm/intel-family.h>
>   #include <asm/apic.h>
>   #include <asm/cpu_device_id.h>
> +#include <asm/hypervisor.h>
>   
>   #include "../perf_event.h"
>   
> @@ -4050,6 +4051,13 @@ static bool check_msr(unsigned long msr, u64 mask)
>   {
>   	u64 val_old, val_new, val_tmp;
>   
> +	/*
> +	 * Disable the check for real HW, so we don't
> +	 * mess up with potentionaly enabled regs.
> +	 */
> +	if (hypervisor_is_type(X86_HYPER_NATIVE))
> +		return true;
> +
>   	/*
>   	 * Read the current value, change it and read it back to see if it
>   	 * matches, this is needed to detect certain hardware emulators
> 

  reply	other threads:[~2019-06-16 20:56 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-14 11:28 [RFC] " Jiri Olsa
2019-06-14 13:33 ` Peter Zijlstra
2019-06-14 13:45 ` Liang, Kan
2019-06-16 14:13   ` [PATCH] " Jiri Olsa
2019-06-16 20:56     ` Vaden, Tom (HPE Server OS Architecture) [this message]
2019-06-17 14:41     ` [tip:perf/core] perf/x86/intel: Disable check_msr for real HW tip-bot for Jiri Olsa
2019-06-21 17:48 ` [RFC] perf/x86/intel: Disable check_msr for real hw Andi Kleen
2019-06-23 22:40   ` Jiri Olsa
2019-06-23 23:44     ` Vaden, Tom (HPE Server OS Architecture)
2019-06-24  8:06     ` Paolo Bonzini
2019-06-24 16:46     ` Andi Kleen
2019-06-24 18:06       ` Jiri Olsa
2019-06-24 18:38         ` Andi Kleen
2019-06-24 18:49           ` Jiri Olsa

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