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* [PATCH] net: dsa: realtek-smi: fix indirect reg access for ports>4
@ 2021-11-26  6:36 luizluca
  2021-11-26  8:12 ` [PATCH v2] net: dsa: realtek-smi: fix indirect reg access for ports>3 luizluca
  0 siblings, 1 reply; 4+ messages in thread
From: luizluca @ 2021-11-26  6:36 UTC (permalink / raw)
  To: netdev; +Cc: linux-kernel, stable, alsi, Luiz Angelo Daros de Luca

From: Luiz Angelo Daros de Luca <luizluca@gmail.com>

This switch family can have up to 8 ports {0..7}. However,
INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK was using 2 bits instead of 3,
dropping the most significant bit during indirect register reads and
writes. Reading or writing ports 5, 6, and 7 registers was actually
manipulating, respectively, ports 0, 1, and 2 registers.

rtl8365mb_phy_{read,write} will now returns -EINVAL if phy is greater
than 7.

Fixes: 4af2950c50c8 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC")
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
 drivers/net/dsa/rtl8365mb.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/net/dsa/rtl8365mb.c b/drivers/net/dsa/rtl8365mb.c
index baaae97283c5..f4414ac74b61 100644
--- a/drivers/net/dsa/rtl8365mb.c
+++ b/drivers/net/dsa/rtl8365mb.c
@@ -107,6 +107,7 @@
 #define RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC	2112
 
 /* Family-specific data and limits */
+#define RTL8365MB_PHYADDRMAX	7
 #define RTL8365MB_NUM_PHYREGS	32
 #define RTL8365MB_PHYREGMAX	(RTL8365MB_NUM_PHYREGS - 1)
 #define RTL8365MB_MAX_NUM_PORTS	(RTL8365MB_CPU_PORT_NUM_8365MB_VC + 1)
@@ -176,7 +177,7 @@
 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG			0x1F01
 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG			0x1F02
 #define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK	GENMASK(4, 0)
-#define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK		GENMASK(6, 5)
+#define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK		GENMASK(7, 5)
 #define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK	GENMASK(11, 8)
 #define   RTL8365MB_PHY_BASE					0x2000
 #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG		0x1F03
@@ -679,6 +680,8 @@ static int rtl8365mb_phy_read(struct realtek_smi *smi, int phy, int regnum)
 	u16 val;
 	int ret;
 
+	if (phy > RTL8365MB_PHYADDRMAX)
+		return -EINVAL;
 	if (regnum > RTL8365MB_PHYREGMAX)
 		return -EINVAL;
 
@@ -704,6 +707,8 @@ static int rtl8365mb_phy_write(struct realtek_smi *smi, int phy, int regnum,
 	u32 ocp_addr;
 	int ret;
 
+	if (phy > RTL8365MB_PHYADDRMAX)
+		return -EINVAL;
 	if (regnum > RTL8365MB_PHYREGMAX)
 		return -EINVAL;
 
-- 
2.33.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH v2] net: dsa: realtek-smi: fix indirect reg access for ports>3
  2021-11-26  6:36 [PATCH] net: dsa: realtek-smi: fix indirect reg access for ports>4 luizluca
@ 2021-11-26  8:12 ` luizluca
  2021-11-26  8:21   ` Greg KH
  2021-11-26  9:34   ` Alvin Šipraga
  0 siblings, 2 replies; 4+ messages in thread
From: luizluca @ 2021-11-26  8:12 UTC (permalink / raw)
  To: netdev; +Cc: linux-kernel, stable, alsi, Luiz Angelo Daros de Luca

From: Luiz Angelo Daros de Luca <luizluca@gmail.com>

This switch family can have up to 8 ports {0..7}. However,
INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK was using 2 bits instead of 3,
dropping the most significant bit during indirect register reads and
writes. Reading or writing ports 4, 5, 6, and 7 registers was actually
manipulating, respectively, ports 0, 1, 2, and 3 registers.

rtl8365mb_phy_{read,write} will now returns -EINVAL if phy is greater
than 7.

v2:
- fix affected ports in commit message

Fixes: 4af2950c50c8 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC")
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
---
 drivers/net/dsa/rtl8365mb.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/net/dsa/rtl8365mb.c b/drivers/net/dsa/rtl8365mb.c
index baaae97283c5..f4414ac74b61 100644
--- a/drivers/net/dsa/rtl8365mb.c
+++ b/drivers/net/dsa/rtl8365mb.c
@@ -107,6 +107,7 @@
 #define RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC	2112
 
 /* Family-specific data and limits */
+#define RTL8365MB_PHYADDRMAX	7
 #define RTL8365MB_NUM_PHYREGS	32
 #define RTL8365MB_PHYREGMAX	(RTL8365MB_NUM_PHYREGS - 1)
 #define RTL8365MB_MAX_NUM_PORTS	(RTL8365MB_CPU_PORT_NUM_8365MB_VC + 1)
@@ -176,7 +177,7 @@
 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG			0x1F01
 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG			0x1F02
 #define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK	GENMASK(4, 0)
-#define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK		GENMASK(6, 5)
+#define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK		GENMASK(7, 5)
 #define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK	GENMASK(11, 8)
 #define   RTL8365MB_PHY_BASE					0x2000
 #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG		0x1F03
@@ -679,6 +680,8 @@ static int rtl8365mb_phy_read(struct realtek_smi *smi, int phy, int regnum)
 	u16 val;
 	int ret;
 
+	if (phy > RTL8365MB_PHYADDRMAX)
+		return -EINVAL;
 	if (regnum > RTL8365MB_PHYREGMAX)
 		return -EINVAL;
 
@@ -704,6 +707,8 @@ static int rtl8365mb_phy_write(struct realtek_smi *smi, int phy, int regnum,
 	u32 ocp_addr;
 	int ret;
 
+	if (phy > RTL8365MB_PHYADDRMAX)
+		return -EINVAL;
 	if (regnum > RTL8365MB_PHYREGMAX)
 		return -EINVAL;
 
-- 
2.33.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v2] net: dsa: realtek-smi: fix indirect reg access for ports>3
  2021-11-26  8:12 ` [PATCH v2] net: dsa: realtek-smi: fix indirect reg access for ports>3 luizluca
@ 2021-11-26  8:21   ` Greg KH
  2021-11-26  9:34   ` Alvin Šipraga
  1 sibling, 0 replies; 4+ messages in thread
From: Greg KH @ 2021-11-26  8:21 UTC (permalink / raw)
  To: luizluca; +Cc: netdev, linux-kernel, stable, alsi

On Fri, Nov 26, 2021 at 05:12:52AM -0300, luizluca@gmail.com wrote:
> From: Luiz Angelo Daros de Luca <luizluca@gmail.com>
> 
> This switch family can have up to 8 ports {0..7}. However,
> INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK was using 2 bits instead of 3,
> dropping the most significant bit during indirect register reads and
> writes. Reading or writing ports 4, 5, 6, and 7 registers was actually
> manipulating, respectively, ports 0, 1, 2, and 3 registers.
> 
> rtl8365mb_phy_{read,write} will now returns -EINVAL if phy is greater
> than 7.
> 
> v2:
> - fix affected ports in commit message
> 
> Fixes: 4af2950c50c8 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC")
> Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
> ---
>  drivers/net/dsa/rtl8365mb.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)

<formletter>

This is not the correct way to submit patches for inclusion in the
stable kernel tree.  Please read:
    https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
for how to do this properly.

</formletter>

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v2] net: dsa: realtek-smi: fix indirect reg access for ports>3
  2021-11-26  8:12 ` [PATCH v2] net: dsa: realtek-smi: fix indirect reg access for ports>3 luizluca
  2021-11-26  8:21   ` Greg KH
@ 2021-11-26  9:34   ` Alvin Šipraga
  1 sibling, 0 replies; 4+ messages in thread
From: Alvin Šipraga @ 2021-11-26  9:34 UTC (permalink / raw)
  To: luizluca; +Cc: linux-kernel, stable, netdev

Hi Luiz,

Thanks for your patch.

You needn't cc the stable list, since rtl8365mb doesn't exist in any 
stable release just yet. If you send a v3, just target net:

[PATCH net v3] net: dsa: ...

Then the fix will land in 5.16. :-)

On 11/26/21 09:12, luizluca@gmail.com wrote:
> From: Luiz Angelo Daros de Luca <luizluca@gmail.com>
> 
> This switch family can have up to 8 ports {0..7}. However,
> INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK was using 2 bits instead of 3,
> dropping the most significant bit during indirect register reads and
> writes. Reading or writing ports 4, 5, 6, and 7 registers was actually
> manipulating, respectively, ports 0, 1, 2, and 3 registers.

Nice catch. Out of curiosity can you share what switch you are testing? 
So far the driver only advertises support for RTL8365MB-VC. Since that 
switch only uses PHY addresses 0~3, it shouldn't be affected by a 
narrower (2-bit) PHYNUM_MASK, right? Are you able to add words to the 
effect of "... now this fixes the driver to work with RTL83xxxx"?

The change is OK except for some comments below:

> 
> rtl8365mb_phy_{read,write} will now returns -EINVAL if phy is greater
> than 7.

I don't think this is really necessary: a valid (device tree) 
configuration should never specify a PHY with address greater than 7. Or 
am I missing something?

> 
> v2:
> - fix affected ports in commit message

The changelog shouldn't end up in the final commit message - please move 
it out in v3.

> 
> Fixes: 4af2950c50c8 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC")
> Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
> ---
>   drivers/net/dsa/rtl8365mb.c | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/dsa/rtl8365mb.c b/drivers/net/dsa/rtl8365mb.c
> index baaae97283c5..f4414ac74b61 100644
> --- a/drivers/net/dsa/rtl8365mb.c
> +++ b/drivers/net/dsa/rtl8365mb.c
> @@ -107,6 +107,7 @@
>   #define RTL8365MB_LEARN_LIMIT_MAX_8365MB_VC	2112
>   
>   /* Family-specific data and limits */
> +#define RTL8365MB_PHYADDRMAX	7
>   #define RTL8365MB_NUM_PHYREGS	32
>   #define RTL8365MB_PHYREGMAX	(RTL8365MB_NUM_PHYREGS - 1)
>   #define RTL8365MB_MAX_NUM_PORTS	(RTL8365MB_CPU_PORT_NUM_8365MB_VC + 1)
> @@ -176,7 +177,7 @@
>   #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG			0x1F01
>   #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG			0x1F02
>   #define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK	GENMASK(4, 0)
> -#define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK		GENMASK(6, 5)
> +#define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK		GENMASK(7, 5)
>   #define   RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK	GENMASK(11, 8)
>   #define   RTL8365MB_PHY_BASE					0x2000
>   #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG		0x1F03
> @@ -679,6 +680,8 @@ static int rtl8365mb_phy_read(struct realtek_smi *smi, int phy, int regnum)
>   	u16 val;
>   	int ret;
>   
> +	if (phy > RTL8365MB_PHYADDRMAX)
> +		return -EINVAL;
>   	if (regnum > RTL8365MB_PHYREGMAX)

If you decide to keep these check, please add a newline after your returns.

>   		return -EINVAL;
>   
> @@ -704,6 +707,8 @@ static int rtl8365mb_phy_write(struct realtek_smi *smi, int phy, int regnum,
>   	u32 ocp_addr;
>   	int ret;
>   
> +	if (phy > RTL8365MB_PHYADDRMAX)
> +		return -EINVAL;
>   	if (regnum > RTL8365MB_PHYREGMAX)
>   		return -EINVAL;
>   
> 


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-11-26  9:36 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-26  6:36 [PATCH] net: dsa: realtek-smi: fix indirect reg access for ports>4 luizluca
2021-11-26  8:12 ` [PATCH v2] net: dsa: realtek-smi: fix indirect reg access for ports>3 luizluca
2021-11-26  8:21   ` Greg KH
2021-11-26  9:34   ` Alvin Šipraga

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