LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
       [not found] ` <20210722094551.15255-10-nancy.lin@mediatek.com>
@ 2021-07-23 10:57   ` Enric Balletbo Serra
       [not found]     ` <692eeb1314da94e28ccc8722b94c7ce8cae6c880.camel@mediatek.com>
  0 siblings, 1 reply; 4+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 10:57 UTC (permalink / raw)
  To: Nancy.Lin
  Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
	jason-jh . lin, singo.chang, linux-kernel, dri-devel,
	Yongqiang Niu, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Matthias Brugger,
	Linux ARM

Hi Nancy,

Thank you for your patch.

Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:46:
>
> Among other features the mmsys driver should implement a reset
> controller to be able to reset different bits from their space.
>

I'm working on a series that does the same, it should be nice if we
can coordinate [1]

[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355

> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
>  drivers/soc/mediatek/mt8195-mmsys.h |  1 +
>  drivers/soc/mediatek/mtk-mmsys.c    | 77 +++++++++++++++++++++++++++++
>  drivers/soc/mediatek/mtk-mmsys.h    |  1 +
>  3 files changed, 79 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 4bdb2087250c..a7f6e275bfe5 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -154,6 +154,7 @@
>  #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT     (1 << 0)
>  #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT       (2 << 0)
>
> +#define MT8195_VDO1_SW0_RST_B           0x1d0
>  #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD        0xe30
>  #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD        0xe40
>  #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD        0xe50
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index d0f4a407f8f8..1ae04efeadab 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -4,10 +4,12 @@
>   * Author: James Liao <jamesjj.liao@mediatek.com>
>   */
>
> +#include <linux/delay.h>
>  #include <linux/device.h>
>  #include <linux/io.h>
>  #include <linux/of_device.h>
>  #include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
>  #include <linux/soc/mediatek/mtk-mmsys.h>
>
>  #include "mtk-mmsys.h"
> @@ -15,6 +17,8 @@
>  #include "mt8183-mmsys.h"
>  #include "mt8195-mmsys.h"
>
> +#define MMSYS_SW_RESET_PER_REG 32
> +
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>         .clk_driver = "clk-mt2701-mm",
>         .routes = mmsys_default_routing_table,
> @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
>         .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
>         .config = mmsys_mt8195_config_table,
>         .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> +       .sw_reset_start = MT8195_VDO1_SW0_RST_B,

That change is interesting and I think I should also take it into
consideration with my series.

>  };
>
>  struct mtk_mmsys {
>         void __iomem *regs;
>         struct cmdq_client_reg cmdq_base;
>         const struct mtk_mmsys_driver_data *data;
> +       spinlock_t lock; /* protects mmsys_sw_rst_b reg */

Seems that mmsys_sw_rst_b reg has different names for different SoCs?
I mean I know that for MT8173 and MT8183 the register is called
mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
So maybe we should update this comment to be more generic.

> +       struct reset_controller_dev rcdev;
>  };
>
>  void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
>  }
>  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
>
> +static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,
> +                                 bool assert)
> +{
> +       struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
> +       unsigned long flags;
> +       u32 reg;
> +       int i;
> +       u32 offset;
> +
> +       offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> +       id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> +
> +       spin_lock_irqsave(&mmsys->lock, flags);
> +
> +       reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
> +
> +       if (assert)
> +               reg &= ~BIT(id);
> +       else
> +               reg |= BIT(id);
> +
> +       writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
> +
> +       spin_unlock_irqrestore(&mmsys->lock, flags);
> +
> +       return 0;
> +}
> +
> +static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> +       return mtk_mmsys_reset_update(rcdev, id, true);
> +}
> +
> +static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> +       return mtk_mmsys_reset_update(rcdev, id, false);
> +}
> +
> +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> +       int ret;
> +
> +       ret = mtk_mmsys_reset_assert(rcdev, id);
> +       if (ret)
> +               return ret;
> +
> +       usleep_range(1000, 1100);
> +

One question that I received in my series, and I couldn't answer
because I don't have the datasheet, is if
is this known to be enough for all IP cores that can be reset by this
controller? Is this time specified in the datasheet?

> +       return mtk_mmsys_reset_deassert(rcdev, id);
> +}
> +
> +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> +       .assert = mtk_mmsys_reset_assert,
> +       .deassert = mtk_mmsys_reset_deassert,
> +       .reset = mtk_mmsys_reset,
> +};
> +
>  static int mtk_mmsys_probe(struct platform_device *pdev)
>  {
>         struct device *dev = &pdev->dev;
> @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
>         if (ret)
>                 dev_dbg(dev, "No mediatek,gce-client-reg!\n");
>  #endif
> +
> +       spin_lock_init(&mmsys->lock);
> +
> +       mmsys->rcdev.owner = THIS_MODULE;
> +       mmsys->rcdev.nr_resets = 64;

Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
MT8183. Can you confirm?

Thanks,
  Enric

> +       mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> +       mmsys->rcdev.of_node = pdev->dev.of_node;
> +       ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
> +               return ret;
> +       }
> +
>         platform_set_drvdata(pdev, mmsys);
>
>         clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 084b1f5f3c88..cc57c3895c51 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
>         const unsigned int num_routes;
>         const struct mtk_mmsys_config *config;
>         const unsigned int num_configs;
> +       u32 sw_reset_start;
>  };
>
>  /*
> --
> 2.18.0
>

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location
       [not found] ` <20210722094551.15255-5-nancy.lin@mediatek.com>
@ 2021-07-23 11:10   ` Enric Balletbo Serra
  0 siblings, 0 replies; 4+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 11:10 UTC (permalink / raw)
  To: Nancy.Lin
  Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
	jason-jh . lin, singo.chang, linux-kernel, dri-devel,
	Yongqiang Niu, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Matthias Brugger,
	Linux ARM

Hi Nancy,

Thank you for your patch

Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de jul.
2021 a les 11:46:
>
> The DT binding includes for reset controllers are located in
> include/dt-bindings/reset/. Move the Mediatek reset constants in there.
>

I think that the patch that introduces mt8195-resets.h into the
reset-controller directory didn't land yet, please sync with the
author of that patch and just put it in the correct place the first
time.

Thanks,
  Enric

> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
>  include/dt-bindings/{reset-controller => reset}/mt8195-resets.h | 0
>  1 file changed, 0 insertions(+), 0 deletions(-)
>  rename include/dt-bindings/{reset-controller => reset}/mt8195-resets.h (100%)
>
> diff --git a/include/dt-bindings/reset-controller/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> similarity index 100%
> rename from include/dt-bindings/reset-controller/mt8195-resets.h
> rename to include/dt-bindings/reset/mt8195-resets.h
> --
> 2.18.0
>

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1
       [not found]     ` <692eeb1314da94e28ccc8722b94c7ce8cae6c880.camel@mediatek.com>
@ 2021-07-28 10:31       ` Enric Balletbo Serra
  0 siblings, 0 replies; 4+ messages in thread
From: Enric Balletbo Serra @ 2021-07-28 10:31 UTC (permalink / raw)
  To: Nancy.Lin
  Cc: CK Hu, Chun-Kuang Hu, srv_heupstream, devicetree, David Airlie,
	jason-jh . lin, singo.chang, linux-kernel, dri-devel,
	Yongqiang Niu, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Matthias Brugger,
	Linux ARM

Hi Nancy,

Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dc., 28 de jul.
2021 a les 8:01:
>
> Hi Enric,
>
> Thanks for your review.
>
> On Fri, 2021-07-23 at 12:57 +0200, Enric Balletbo Serra wrote:
> > Hi Nancy,
> >
> > Thank you for your patch.
> >
> > Missatge de Nancy.Lin <nancy.lin@mediatek.com> del dia dj., 22 de
> > jul.
> > 2021 a les 11:46:
> > >
> > > Among other features the mmsys driver should implement a reset
> > > controller to be able to reset different bits from their space.
> > >
> >
> > I'm working on a series that does the same, it should be nice if we
> > can coordinate [1]
> >
> > [1]
> > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=515355__;!!CTRNKA9wMg0ARbw!xP6Ko9hF-3KasGgr7-8Aby_tCwiU2M6gFBAngDLVcJjzooj-MEeTcNG8cf2e9wGb$
> >
> >
> OK, I will add this series to my reference base in the next patch
> revision.
>
> > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > > ---
> > >  drivers/soc/mediatek/mt8195-mmsys.h |  1 +
> > >  drivers/soc/mediatek/mtk-mmsys.c    | 77
> > > +++++++++++++++++++++++++++++
> > >  drivers/soc/mediatek/mtk-mmsys.h    |  1 +
> > >  3 files changed, 79 insertions(+)
> > >
> > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > > b/drivers/soc/mediatek/mt8195-mmsys.h
> > > index 4bdb2087250c..a7f6e275bfe5 100644
> > > --- a/drivers/soc/mediatek/mt8195-mmsys.h
> > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > > @@ -154,6 +154,7 @@
> > >  #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT     (1
> > > << 0)
> > >  #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT       (2
> > > << 0)
> > >
> > > +#define MT8195_VDO1_SW0_RST_B           0x1d0
> > >  #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD        0xe30
> > >  #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD        0xe40
> > >  #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD        0xe50
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > > b/drivers/soc/mediatek/mtk-mmsys.c
> > > index d0f4a407f8f8..1ae04efeadab 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > > @@ -4,10 +4,12 @@
> > >   * Author: James Liao <jamesjj.liao@mediatek.com>
> > >   */
> > >
> > > +#include <linux/delay.h>
> > >  #include <linux/device.h>
> > >  #include <linux/io.h>
> > >  #include <linux/of_device.h>
> > >  #include <linux/platform_device.h>
> > > +#include <linux/reset-controller.h>
> > >  #include <linux/soc/mediatek/mtk-mmsys.h>
> > >
> > >  #include "mtk-mmsys.h"
> > > @@ -15,6 +17,8 @@
> > >  #include "mt8183-mmsys.h"
> > >  #include "mt8195-mmsys.h"
> > >
> > > +#define MMSYS_SW_RESET_PER_REG 32
> > > +
> > >  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > > = {
> > >         .clk_driver = "clk-mt2701-mm",
> > >         .routes = mmsys_default_routing_table,
> > > @@ -65,12 +69,15 @@ static const struct mtk_mmsys_driver_data
> > > mt8195_vdosys1_driver_data = {
> > >         .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > >         .config = mmsys_mt8195_config_table,
> > >         .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> > > +       .sw_reset_start = MT8195_VDO1_SW0_RST_B,
> >
> > That change is interesting and I think I should also take it into
> > consideration with my series.
> >
> > >  };
> > >
> > >  struct mtk_mmsys {
> > >         void __iomem *regs;
> > >         struct cmdq_client_reg cmdq_base;
> > >         const struct mtk_mmsys_driver_data *data;
> > > +       spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> >
> > Seems that mmsys_sw_rst_b reg has different names for different SoCs?
> > I mean I know that for MT8173 and MT8183 the register is called
> > mmsys_sw0_rst_b but looks like for MT8195 the name is vdo1_sw0_rst_b?
> > So maybe we should update this comment to be more generic.
> >
> Yes, the name of MT8195 vdosys1 sw reset is called VDOSYS1_SW0_RST_B
> and the name of vdosys0 sw reset is called GLOBAL0_SW0_RST_B. They have
> a different name. Maybe we can change the comment to "protects mmsys sw
> reset reg".
>
> > >
>
> > > +       struct reset_controller_dev rcdev;
> > >  };
> > >
> > >  void mtk_mmsys_ddp_connect(struct device *dev,
> > > @@ -148,6 +155,63 @@ void mtk_mmsys_ddp_config(struct device *dev,
> > > enum mtk_mmsys_config_type config,
> > >  }
> > >  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> > >
> > > +static int mtk_mmsys_reset_update(struct reset_controller_dev
> > > *rcdev, unsigned long id,
> > > +                                 bool assert)
> > > +{
> > > +       struct mtk_mmsys *mmsys = container_of(rcdev, struct
> > > mtk_mmsys, rcdev);
> > > +       unsigned long flags;
> > > +       u32 reg;
> > > +       int i;
> > > +       u32 offset;
> > > +
> > > +       offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> > > +       id = 1 << (id % MMSYS_SW_RESET_PER_REG);
> > > +
> > > +       spin_lock_irqsave(&mmsys->lock, flags);
> > > +
> > > +       reg = readl_relaxed(mmsys->regs + mmsys->data-
> > > >sw_reset_start + offset);
> > > +
> > > +       if (assert)
> > > +               reg &= ~BIT(id);
> > > +       else
> > > +               reg |= BIT(id);
> > > +
> > > +       writel_relaxed(reg, mmsys->regs + mmsys->data-
> > > >sw_reset_start + offset);
> > > +
> > > +       spin_unlock_irqrestore(&mmsys->lock, flags);
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static int mtk_mmsys_reset_assert(struct reset_controller_dev
> > > *rcdev, unsigned long id)
> > > +{
> > > +       return mtk_mmsys_reset_update(rcdev, id, true);
> > > +}
> > > +
> > > +static int mtk_mmsys_reset_deassert(struct reset_controller_dev
> > > *rcdev, unsigned long id)
> > > +{
> > > +       return mtk_mmsys_reset_update(rcdev, id, false);
> > > +}
> > > +
> > > +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev,
> > > unsigned long id)
> > > +{
> > > +       int ret;
> > > +
> > > +       ret = mtk_mmsys_reset_assert(rcdev, id);
> > > +       if (ret)
> > > +               return ret;
> > > +
> > > +       usleep_range(1000, 1100);
> > > +
> >
> > One question that I received in my series, and I couldn't answer
> > because I don't have the datasheet, is if
> > is this known to be enough for all IP cores that can be reset by this
> > controller? Is this time specified in the datasheet?
>
> It only takes few cycles for the reset. The 1000us is enough for the
> reset to take effect.
>

Saying enough looks to me that 1000us is a random number, is there any
specific real number in the datasheet?

Note that I'm not against it, just want to make sure the number makes sense.


> > > +       return mtk_mmsys_reset_deassert(rcdev, id);
> > > +}
> > > +
> > > +static const struct reset_control_ops mtk_mmsys_reset_ops = {
> > > +       .assert = mtk_mmsys_reset_assert,
> > > +       .deassert = mtk_mmsys_reset_deassert,
> > > +       .reset = mtk_mmsys_reset,
> > > +};
> > > +
> > >  static int mtk_mmsys_probe(struct platform_device *pdev)
> > >  {
> > >         struct device *dev = &pdev->dev;
> > > @@ -174,6 +238,19 @@ static int mtk_mmsys_probe(struct
> > > platform_device *pdev)
> > >         if (ret)
> > >                 dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> > >  #endif
> > > +
> > > +       spin_lock_init(&mmsys->lock);
> > > +
> > > +       mmsys->rcdev.owner = THIS_MODULE;
> > > +       mmsys->rcdev.nr_resets = 64;
> >
> > Is the number of resets 64 for MT8195? I think is 32 for MT8173 and
> > MT8183. Can you confirm?
> >
> > Thanks,
> >   Enric
> >
> The number of resets in MT8195 vdosys1 is 64 (43 resets are used, 21
> are not used).
>

Ok, thanks for the information.

> > > +       mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
> > > +       mmsys->rcdev.of_node = pdev->dev.of_node;
> > > +       ret = devm_reset_controller_register(&pdev->dev, &mmsys-
> > > >rcdev);
> > > +       if (ret) {
> > > +               dev_err(&pdev->dev, "Couldn't register mmsys reset
> > > controller: %d\n", ret);
> > > +               return ret;
> > > +       }
> > > +
> > >         platform_set_drvdata(pdev, mmsys);
> > >
> > >         clks = platform_device_register_data(&pdev->dev, mmsys-
> > > >data->clk_driver,
> > > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > > b/drivers/soc/mediatek/mtk-mmsys.h
> > > index 084b1f5f3c88..cc57c3895c51 100644
> > > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > > @@ -87,6 +87,7 @@ struct mtk_mmsys_driver_data {
> > >         const unsigned int num_routes;
> > >         const struct mtk_mmsys_config *config;
> > >         const unsigned int num_configs;
> > > +       u32 sw_reset_start;
> > >  };
> > >
> > >  /*
> > > --
> > > 2.18.0
> > >

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
       [not found] ` <20210722094551.15255-9-nancy.lin@mediatek.com>
@ 2021-08-06 15:30   ` Matthias Brugger
  0 siblings, 0 replies; 4+ messages in thread
From: Matthias Brugger @ 2021-08-06 15:30 UTC (permalink / raw)
  To: Nancy.Lin, CK Hu
  Cc: Chun-Kuang Hu, Philipp Zabel, David Airlie, Daniel Vetter,
	Rob Herring, jason-jh . lin, Yongqiang Niu, dri-devel,
	linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
	singo.chang, srv_heupstream



On 22/07/2021 11:45, Nancy.Lin wrote:
> Add mmsys config API.

This patch is doing a lot of things, it adds a "config" and it adds cmdq
support. Please explain better in the commit message what the config is for.
Please add comments to the different values of struct mtk_mmsys_config.

I understand that cmdq is optional, so please make addition to cmdq a separate
patch.
I'm a bit puzzled about that fact, can you please explain who you get the HW to
behave the same way when you write the same value and offset to mmsys-regs and
via cmdq.

Thanks,
Matthias

> 
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
>  drivers/soc/mediatek/mt8195-mmsys.h    | 38 ++++++++++++++++++++
>  drivers/soc/mediatek/mtk-mmsys.c       | 50 ++++++++++++++++++++++++++
>  drivers/soc/mediatek/mtk-mmsys.h       | 10 ++++++
>  include/linux/soc/mediatek/mtk-mmsys.h | 18 ++++++++++
>  4 files changed, 116 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 104ba575f765..4bdb2087250c 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -154,6 +154,18 @@
>  #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT	(1 << 0)
>  #define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT	(2 << 0)
>  
> +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD	0xe30
> +#define MT8195_VDO1_MERGE1_ASYNC_CFG_WD	0xe40
> +#define MT8195_VDO1_MERGE2_ASYNC_CFG_WD	0xe50
> +#define MT8195_VDO1_MERGE3_ASYNC_CFG_WD	0xe60
> +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD	0xe70
> +#define MT8195_VDO1_HDR_TOP_CFG		0xd00
> +#define MT8195_VDO1_MIXER_IN1_ALPHA	0xd30
> +#define MT8195_VDO1_MIXER_IN2_ALPHA	0xd34
> +#define MT8195_VDO1_MIXER_IN3_ALPHA	0xd38
> +#define MT8195_VDO1_MIXER_IN4_ALPHA	0xd3c
> +#define MT8195_VDO1_MIXER_IN4_PAD	0xd4c
> +
>  static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
>  	{
>  		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> @@ -261,4 +273,30 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
>  	}
>  };
>  
> +static const struct mtk_mmsys_config mmsys_mt8195_config_table[] = {
> +	{ MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> +	{ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 0, MT8195_VDO1_MERGE0_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> +	{ MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> +	{ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 1, MT8195_VDO1_MERGE1_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> +	{ MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> +	{ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 2, MT8195_VDO1_MERGE2_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> +	{ MMSYS_CONFIG_MERGE_ASYNC_WIDTH, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> +	{ MMSYS_CONFIG_MERGE_ASYNC_HEIGHT, 3, MT8195_VDO1_MERGE3_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> +	{ MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(13, 0), 0},
> +	{ MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT, 0, MT8195_VDO1_HDRBE_ASYNC_CFG_WD, GENMASK(29, 16), 16},
> +	{ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(8, 0), 0},
> +	{ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 1, MT8195_VDO1_MIXER_IN1_ALPHA, GENMASK(24, 16), 16},
> +	{ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(8, 0), 0},
> +	{ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 2, MT8195_VDO1_MIXER_IN2_ALPHA, GENMASK(24, 16), 16},
> +	{ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(8, 0), 0},
> +	{ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 3, MT8195_VDO1_MIXER_IN3_ALPHA, GENMASK(24, 16), 16},
> +	{ MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(8, 0), 0},
> +	{ MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, 4, MT8195_VDO1_MIXER_IN4_ALPHA, GENMASK(24, 16), 16},
> +	{ MMSYS_CONFIG_MIXER_IN_CH_SWAP, 4, MT8195_VDO1_MIXER_IN4_PAD, GENMASK(4, 4), 4},
> +	{ MMSYS_CONFIG_HDR_ALPHA_SEL, 1, MT8195_VDO1_HDR_TOP_CFG, GENMASK(20, 20), 20},
> +	{ MMSYS_CONFIG_HDR_ALPHA_SEL, 2, MT8195_VDO1_HDR_TOP_CFG, GENMASK(21, 21), 21},
> +	{ MMSYS_CONFIG_HDR_ALPHA_SEL, 3, MT8195_VDO1_HDR_TOP_CFG, GENMASK(22, 22), 22},
> +	{ MMSYS_CONFIG_HDR_ALPHA_SEL, 4, MT8195_VDO1_HDR_TOP_CFG, GENMASK(23, 23), 23},
> +};
> +
>  #endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 9e31aad6c5c8..d0f4a407f8f8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -63,10 +63,13 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
>  	.clk_driver = "clk-mt8195-vdo1",
>  	.routes = mmsys_mt8195_routing_table,
>  	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +	.config = mmsys_mt8195_config_table,
> +	.num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
>  };
>  
>  struct mtk_mmsys {
>  	void __iomem *regs;
> +	struct cmdq_client_reg cmdq_base;
>  	const struct mtk_mmsys_driver_data *data;
>  };
>  
> @@ -104,6 +107,47 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>  }
>  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>  
> +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> +			  u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
> +{
> +	struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> +	const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
> +	u32 reg_val;
> +	u32 mask;
> +	u32 offset;
> +	int i;
> +
> +	if (!mmsys->data->num_configs)
> +		return;
> +
> +	for (i = 0; i < mmsys->data->num_configs; i++)
> +		if (config == mmsys_config[i].config && id == mmsys_config[i].id)
> +			break;
> +
> +	if (i == mmsys->data->num_configs)
> +		return;
> +
> +	offset = mmsys_config[i].addr;
> +	mask = mmsys_config[i].mask;
> +	reg_val = val << mmsys_config[i].shift;
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +	if (cmdq_pkt && mmsys->cmdq_base.size) {
> +		cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
> +				    mmsys->cmdq_base.offset + offset, reg_val,
> +				    mask);
> +	} else {
> +#endif
> +		u32 tmp = readl(mmsys->regs + offset);
> +
> +		tmp = (tmp & ~mask) | reg_val;
> +		writel(tmp, mmsys->regs + offset);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +	}
> +#endif
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
> +
>  static int mtk_mmsys_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -124,6 +168,12 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
>  	}
>  
>  	mmsys->data = of_device_get_match_data(&pdev->dev);
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +	ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> +	if (ret)
> +		dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> +#endif
>  	platform_set_drvdata(pdev, mmsys);
>  
>  	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index a760a34e6eca..084b1f5f3c88 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -73,10 +73,20 @@ struct mtk_mmsys_routes {
>  	u32 val;
>  };
>  
> +struct mtk_mmsys_config {
> +	enum mtk_mmsys_config_type config;
> +	u32 id;
> +	u32 addr;
> +	u32 mask;
> +	u32 shift;
> +};
> +
>  struct mtk_mmsys_driver_data {
>  	const char *clk_driver;
>  	const struct mtk_mmsys_routes *routes;
>  	const unsigned int num_routes;
> +	const struct mtk_mmsys_config *config;
> +	const unsigned int num_configs;
>  };
>  
>  /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 338c71570aeb..ba3925661cc9 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -6,6 +6,10 @@
>  #ifndef __MTK_MMSYS_H
>  #define __MTK_MMSYS_H
>  
> +#include <linux/mailbox_controller.h>
> +#include <linux/mailbox/mtk-cmdq-mailbox.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
>  enum mtk_ddp_comp_id;
>  struct device;
>  
> @@ -54,6 +58,17 @@ enum mtk_ddp_comp_id {
>  	DDP_COMPONENT_ID_MAX,
>  };
>  
> +enum mtk_mmsys_config_type {
> +	MMSYS_CONFIG_MERGE_ASYNC_WIDTH,
> +	MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,
> +	MMSYS_CONFIG_HDR_BE_ASYNC_WIDTH,
> +	MMSYS_CONFIG_HDR_BE_ASYNC_HEIGHT,
> +	MMSYS_CONFIG_HDR_ALPHA_SEL,
> +	MMSYS_CONFIG_MIXER_IN_ALPHA_ODD,
> +	MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN,
> +	MMSYS_CONFIG_MIXER_IN_CH_SWAP,
> +};
> +
>  void mtk_mmsys_ddp_connect(struct device *dev,
>  			   enum mtk_ddp_comp_id cur,
>  			   enum mtk_ddp_comp_id next);
> @@ -62,4 +77,7 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>  			      enum mtk_ddp_comp_id cur,
>  			      enum mtk_ddp_comp_id next);
>  
> +void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> +			  u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
> +
>  #endif /* __MTK_MMSYS_H */
> 

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-08-06 15:30 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
     [not found] <20210722094551.15255-1-nancy.lin@mediatek.com>
     [not found] ` <20210722094551.15255-10-nancy.lin@mediatek.com>
2021-07-23 10:57   ` [PATCH v2 09/14] soc: mediatek: mmsys: Add reset controller support for MT8195 vdosys1 Enric Balletbo Serra
     [not found]     ` <692eeb1314da94e28ccc8722b94c7ce8cae6c880.camel@mediatek.com>
2021-07-28 10:31       ` Enric Balletbo Serra
     [not found] ` <20210722094551.15255-5-nancy.lin@mediatek.com>
2021-07-23 11:10   ` [PATCH v2 04/14] dt-bindings: reset: mt8195: Move reset controller constants into common location Enric Balletbo Serra
     [not found] ` <20210722094551.15255-9-nancy.lin@mediatek.com>
2021-08-06 15:30   ` [PATCH v2 08/14] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Matthias Brugger

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).