From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2163C04AB7 for ; Tue, 14 May 2019 05:27:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A44CE21655 for ; Tue, 14 May 2019 05:27:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="GWsXtVm0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726678AbfENF1N (ORCPT ); Tue, 14 May 2019 01:27:13 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:15437 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725562AbfENF1N (ORCPT ); Tue, 14 May 2019 01:27:13 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 13 May 2019 22:27:19 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 13 May 2019 22:27:12 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 13 May 2019 22:27:12 -0700 Received: from [10.24.47.172] (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 14 May 2019 05:27:06 +0000 Subject: Re: [PATCH V6 06/15] dt-bindings: PCI: designware: Add binding for CDM register check To: Rob Herring CC: , , , , , , , , , , , , , , , , , , References: <20190513050626.14991-1-vidyas@nvidia.com> <20190513050626.14991-7-vidyas@nvidia.com> <20190513151038.GA30653@bogus> X-Nvconfidentiality: public From: Vidya Sagar Message-ID: Date: Tue, 14 May 2019 10:57:04 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190513151038.GA30653@bogus> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1557811639; bh=Dq8qnb1ysO5RsRvY1YBGjeDlfEbkkUSeJAsfidt5wpQ=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=GWsXtVm0irwfCt46TdsXdVGHhKZ9q888BDruFt5aAi9LxMNGaaumFAq7MIX/j2Ed+ EeQx0ggPp1kqnzq/M1zeYmDAU3f8dgCu43hjNwZbLbJeJE3BvFxQ/hjLwBUg9SXgYs Ao0UdVfoAkAHe0h9G+rpfQp4l8Kxl4IoRj/KMr4ddnaOiHzjKpTq24d4kUt2cN86fY zLQ4wEo/Sqj/8v9ys5GwXNjXNVH+W+xtI8/CiItwIw2tyXDwaIriMmsxGpWclU9NHg IwPPAp7xxXyay8xLmm+kolhyLoQemXTdisK6RM2j7m3CDMR+71rFljtXg3ka8QLUsa ym5Aix8T+vEFg== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/13/2019 8:40 PM, Rob Herring wrote: > On Mon, May 13, 2019 at 10:36:17AM +0530, Vidya Sagar wrote: >> Add support to enable CDM (Configuration Dependent Module) registers check >> for any data corruption. CDM registers include standard PCIe configuration >> space registers, Port Logic registers and iATU and DMA registers. >> Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook >> Version 4.90a >> >> Signed-off-by: Vidya Sagar >> --- >> Changes since [v5]: >> * None >> >> Changes since [v4]: >> * None >> >> Changes since [v3]: >> * None >> >> Changes since [v2]: >> * Changed flag name from 'cdm-check' to 'enable-cdm-check' >> * Added info about Port Logic and DMA registers being part of CDM >> >> Changes since [v1]: >> * This is a new patch in v2 series >> >> Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt >> index 5561a1c060d0..85b872c42a9f 100644 >> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt >> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt >> @@ -34,6 +34,11 @@ Optional properties: >> - clock-names: Must include the following entries: >> - "pcie" >> - "pcie_bus" >> +- enable-cdm-check: This is a boolean property and if present enables >> + automatic checking of CDM (Configuration Dependent Module) registers >> + for data corruption. CDM registers include standard PCIe configuration >> + space registers, Port Logic registers, DMA and iATU (internal Address >> + Translation Unit) registers. > > snps,enable-cdm-check Ok. Done. > >> RC mode: >> - num-viewport: number of view ports configured in hardware. If a platform >> does not specify it, the driver assumes 2. >> -- >> 2.17.1 >>