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From: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
To: bhelgaas@google.com, lorenzo.pieralisi@arm.com,
	Joao.Pinto@synopsys.com, jingoohan1@gmail.com, kishon@ti.com,
	robh+dt@kernel.org, mark.rutland@arm.com
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com
Subject: [PATCH v4 09/10] PCI: dwc: Small computation improvement
Date: Mon, 16 Apr 2018 15:37:57 +0100	[thread overview]
Message-ID: <beb7d198eb607fa8fc411a73c2997374dc18328c.1523881182.git.gustavo.pimentel@synopsys.com> (raw)
In-Reply-To: <cover.1523881182.git.gustavo.pimentel@synopsys.com>
In-Reply-To: <cover.1523881182.git.gustavo.pimentel@synopsys.com>

Replaces a simple division by 2 to a right shift rotation of 1 bit.

Probably any recent and decent compiler does this kind of substitution
in order to improve code performance. Nevertheless it's a coding good
practice whenever there is a division / multiplication by multiple of 2
to replace it by the equivalent operation in this case, the shift
rotation.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Changes v3->v4:
- Added a small explication to the log description.

 drivers/pci/dwc/pcie-designware-host.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 5a23f78..fc55fde 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -332,8 +332,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
 
 	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
 	if (cfg_res) {
-		pp->cfg0_size = resource_size(cfg_res) / 2;
-		pp->cfg1_size = resource_size(cfg_res) / 2;
+		pp->cfg0_size = resource_size(cfg_res) >> 1;
+		pp->cfg1_size = resource_size(cfg_res) >> 1;
 		pp->cfg0_base = cfg_res->start;
 		pp->cfg1_base = cfg_res->start + pp->cfg0_size;
 	} else if (!pp->va_cfg0_base) {
@@ -377,8 +377,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
 			break;
 		case 0:
 			pp->cfg = win->res;
-			pp->cfg0_size = resource_size(pp->cfg) / 2;
-			pp->cfg1_size = resource_size(pp->cfg) / 2;
+			pp->cfg0_size = resource_size(pp->cfg) >> 1;
+			pp->cfg1_size = resource_size(pp->cfg) >> 1;
 			pp->cfg0_base = pp->cfg->start;
 			pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
 			break;
-- 
2.7.4

  parent reply	other threads:[~2018-04-16 14:38 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-16 14:37 [PATCH v4 00/10] Designware EP support and code clean up Gustavo Pimentel
2018-04-16 14:37 ` [PATCH v4 01/10] bindings: PCI: designware: Example update Gustavo Pimentel
2018-04-16 21:39   ` Rob Herring
2018-04-17 13:47     ` Gustavo Pimentel
2018-04-16 14:37 ` [PATCH v4 02/10] PCI: dwc: Add support for endpoint mode Gustavo Pimentel
2018-04-17  9:17   ` Kishon Vijay Abraham I
2018-04-16 14:37 ` [PATCH v4 03/10] PCI: endpoint: functions/pci-epf-test: Add second entry Gustavo Pimentel
2018-04-17  9:19   ` Kishon Vijay Abraham I
2018-04-17  9:21     ` Kishon Vijay Abraham I
2018-04-16 14:37 ` [PATCH v4 04/10] bindings: PCI: designware: Add support for the EP in Designware driver Gustavo Pimentel
2018-04-16 21:43   ` Rob Herring
2018-04-17 13:33     ` Gustavo Pimentel
2018-04-16 14:37 ` [PATCH v4 05/10] PCI: Adds device ID for Synopsys Sample Endpoint Gustavo Pimentel
2018-04-16 14:37 ` [PATCH v4 06/10] misc: pci_endpoint_test: Add designware EP entry Gustavo Pimentel
2018-04-17  9:22   ` Kishon Vijay Abraham I
2018-04-16 14:37 ` [PATCH v4 07/10] PCI: dwc: Define maximum number of vectors Gustavo Pimentel
2018-04-16 14:37 ` [PATCH v4 08/10] PCI: dwc: Replace lower into upper case characters Gustavo Pimentel
2018-04-16 14:37 ` Gustavo Pimentel [this message]
2018-04-16 14:37 ` [PATCH v4 10/10] PCI: dwc: Replace magic number by defines Gustavo Pimentel

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