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From: Julien Thierry <julien.thierry@arm.com>
To: Sudeep Holla <sudeep.holla@arm.com>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	Christoffer Dall <christoffer.dall@arm.com>,
	Marc Zyngier <marc.zyngier@arm.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Pouloze <suzuki.poulose@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>
Subject: Re: [PATCH v2 05/15] arm64: KVM: add access handler for SPE system registers
Date: Fri, 24 May 2019 12:36:24 +0100	[thread overview]
Message-ID: <c45323a8-92e4-e406-381b-2084e222a870@arm.com> (raw)
In-Reply-To: <20190523103502.25925-6-sudeep.holla@arm.com>

Hi Sudeep,

On 23/05/2019 11:34, Sudeep Holla wrote:
> SPE Profiling Buffer owning EL is configurable and when MDCR_EL2.E2PB
> is configured to provide buffer ownership to EL1, the control registers
> are trapped.
> 
> Add access handlers for the Statistical Profiling Extension(SPE)
> Profiling Buffer controls registers. This is need to support profiling
> using SPE in the guests.
> 
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
>  arch/arm64/include/asm/kvm_host.h | 13 ++++++++++++
>  arch/arm64/kvm/sys_regs.c         | 35 +++++++++++++++++++++++++++++++
>  include/kvm/arm_spe.h             | 15 +++++++++++++
>  3 files changed, 63 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index 611a4884fb6c..559aa6931291 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -147,6 +147,19 @@ enum vcpu_sysreg {
>  	MDCCINT_EL1,	/* Monitor Debug Comms Channel Interrupt Enable Reg */
>  	DISR_EL1,	/* Deferred Interrupt Status Register */
>  
> +	/* Statistical Profiling Extension Registers */
> +
> +	PMSCR_EL1,
> +	PMSICR_EL1,
> +	PMSIRR_EL1,
> +	PMSFCR_EL1,
> +	PMSEVFR_EL1,
> +	PMSLATFR_EL1,
> +	PMSIDR_EL1,
> +	PMBLIMITR_EL1,
> +	PMBPTR_EL1,
> +	PMBSR_EL1,
> +
>  	/* Performance Monitors Registers */
>  	PMCR_EL0,	/* Control Register */
>  	PMSELR_EL0,	/* Event Counter Selection Register */
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 857b226bcdde..dbf5056828d3 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -646,6 +646,30 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>  	__vcpu_sys_reg(vcpu, PMCR_EL0) = val;
>  }
>  
> +static bool access_pmsb_val(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> +			    const struct sys_reg_desc *r)
> +{
> +	if (p->is_write)
> +		vcpu_write_sys_reg(vcpu, p->regval, r->reg);
> +	else
> +		p->regval = vcpu_read_sys_reg(vcpu, r->reg);
> +
> +	return true;
> +}
> +
> +static void reset_pmsb_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> +{
> +	if (!kvm_arm_support_spe_v1()) {
> +		__vcpu_sys_reg(vcpu, r->reg) = 0;
> +		return;
> +	}
> +
> +	if (r->reg == PMSIDR_EL1)

If only PMSIDR_EL1 has a non-zero reset value, it feels a bit weird to
share the reset function for all these registers.

I would suggest only having a reset_pmsidr() function, and just use
reset_val() with sys_reg_desc->val set to 0 for all the others.

> +		__vcpu_sys_reg(vcpu, r->reg) = read_sysreg_s(SYS_PMSIDR_EL1);
> +	else
> +		__vcpu_sys_reg(vcpu, r->reg) = 0;
> +}
> +
>  static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
>  {
>  	u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
> @@ -1513,6 +1537,17 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>  	{ SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
>  	{ SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
>  
> +	{ SYS_DESC(SYS_PMSCR_EL1), access_pmsb_val, reset_pmsb_val, PMSCR_EL1 },
> +	{ SYS_DESC(SYS_PMSICR_EL1), access_pmsb_val, reset_pmsb_val, PMSICR_EL1 },
> +	{ SYS_DESC(SYS_PMSIRR_EL1), access_pmsb_val, reset_pmsb_val, PMSIRR_EL1 },
> +	{ SYS_DESC(SYS_PMSFCR_EL1), access_pmsb_val, reset_pmsb_val, PMSFCR_EL1 },
> +	{ SYS_DESC(SYS_PMSEVFR_EL1), access_pmsb_val, reset_pmsb_val, PMSEVFR_EL1},
> +	{ SYS_DESC(SYS_PMSLATFR_EL1), access_pmsb_val, reset_pmsb_val, PMSLATFR_EL1 },
> +	{ SYS_DESC(SYS_PMSIDR_EL1), access_pmsb_val, reset_pmsb_val, PMSIDR_EL1 },
> +	{ SYS_DESC(SYS_PMBLIMITR_EL1), access_pmsb_val, reset_pmsb_val, PMBLIMITR_EL1 },
> +	{ SYS_DESC(SYS_PMBPTR_EL1), access_pmsb_val, reset_pmsb_val, PMBPTR_EL1 },
> +	{ SYS_DESC(SYS_PMBSR_EL1), access_pmsb_val, reset_pmsb_val, PMBSR_EL1 },
> +
>  	{ SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
>  	{ SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 },
>  
> diff --git a/include/kvm/arm_spe.h b/include/kvm/arm_spe.h
> index 8c96bdfad6ac..2440ff02f747 100644
> --- a/include/kvm/arm_spe.h
> +++ b/include/kvm/arm_spe.h
> @@ -8,6 +8,7 @@
>  
>  #include <uapi/linux/kvm.h>
>  #include <linux/kvm_host.h>
> +#include <linux/cpufeature.h>
>  
>  struct kvm_spe {
>  	int irq;
> @@ -15,4 +16,18 @@ struct kvm_spe {
>  	bool created; /* SPE KVM instance is created, may not be ready yet */
>  };
>  
> +#ifdef CONFIG_KVM_ARM_SPE
> +
> +static inline bool kvm_arm_support_spe_v1(void)
> +{
> +	u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
> +
> +	return !!cpuid_feature_extract_unsigned_field(dfr0,
> +						      ID_AA64DFR0_PMSVER_SHIFT);
> +}
> +#else
> +
> +#define kvm_arm_support_spe_v1()	(false)
> +#endif /* CONFIG_KVM_ARM_SPE */
> +
>  #endif /* __ASM_ARM_KVM_SPE_H */
> 

Cheers,

-- 
Julien Thierry

  reply	other threads:[~2019-05-24 11:36 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-23 10:34 [PATCH 00/15] arm64: KVM: add SPE profiling support for guest Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 01/15] KVM: arm64: add {read,write}_sysreg_elx_s versions for new registers Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 02/15] dt-bindings: ARM SPE: highlight the need for PPI partitions on heterogeneous systems Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 03/15] arm64: KVM: reset E2PB correctly in MDCR_EL2 when exiting the guest(VHE) Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 04/15] arm64: KVM: define SPE data structure for each vcpu Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 05/15] arm64: KVM: add access handler for SPE system registers Sudeep Holla
2019-05-24 11:36   ` Julien Thierry [this message]
2019-05-24 14:12     ` Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 06/15] arm64: KVM/VHE: enable the use PMSCR_EL12 on VHE systems Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 07/15] arm64: KVM: split debug save restore across vm/traps activation Sudeep Holla
2019-05-28  8:18   ` Julien Thierry
2019-05-23 10:34 ` [PATCH v2 08/15] arm64: KVM/debug: drop pmscr_el1 and use sys_regs[PMSCR_EL1] in kvm_cpu_context Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 09/15] arm64: KVM: add support to save/restore SPE profiling buffer controls Sudeep Holla
2019-05-29  8:26   ` Julien Thierry
2019-05-23 10:34 ` [PATCH v2 10/15] arm64: KVM: enable conditional save/restore full " Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 11/15] arm64: KVM/debug: trap all accesses to SPE controls at EL1 Sudeep Holla
2019-05-23 10:34 ` [PATCH v2 12/15] KVM: arm64: add a new vcpu device control group for SPEv1 Sudeep Holla
2019-05-24 10:37   ` Marc Zyngier
2019-05-24 11:21     ` Sudeep Holla
2019-05-24 12:07       ` Marc Zyngier
2019-05-23 10:35 ` [PATCH v2 13/15] KVM: arm64: enable SPE support Sudeep Holla
2019-05-23 10:35 ` [PATCH v2 14/15][KVMTOOL] update_headers: Sync kvm UAPI headers with linux v5.2-rc1 Sudeep Holla
2019-05-23 10:35 ` [PATCH v2 15/15][KVMTOOL] kvm: add a vcpu feature for SPEv1 support Sudeep Holla

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