LKML Archive on lore.kernel.org
help / color / mirror / Atom feed
From: Stefan Agner <stefan@agner.ch>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>,
	Dmitry Osipenko <digetx@gmail.com>,
	dwmw2@infradead.org, computersforpeace@gmail.com,
	marek.vasut@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
	benjamin.lindqvist@endian.se, pgaikwad@nvidia.com,
	dev@lynxeye.de, mirza.krak@gmail.com, richard@nod.at,
	pdeschrijver@nvidia.com, linux-kernel@vger.kernel.org,
	krzk@kernel.org, jonathanh@nvidia.com,
	devicetree@vger.kernel.org, linux-mtd@lists.infradead.org,
	marcel@ziswiler.com, miquel.raynal@bootlin.com,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v3 3/6] mtd: rawnand: tegra: add devicetree binding
Date: Wed, 06 Jun 2018 14:14:23 +0200	[thread overview]
Message-ID: <c687fc59e2662d07568f94efb55bc250@agner.ch> (raw)
In-Reply-To: <20180606110735.GM11810@ulmo>

On 06.06.2018 13:07, Thierry Reding wrote:
> On Wed, Jun 06, 2018 at 12:45:40PM +0200, Boris Brezillon wrote:
>> Hi Thierry,
>>
>> On Wed, 6 Jun 2018 12:39:03 +0200
>> Thierry Reding <thierry.reding@gmail.com> wrote:
>>
>> > On Tue, Jun 05, 2018 at 11:19:14PM +0300, Dmitry Osipenko wrote:
>> > > On 01.06.2018 10:30, Boris Brezillon wrote:
>> > > > On Fri,  1 Jun 2018 00:16:34 +0200
>> > > > Stefan Agner <stefan@agner.ch> wrote:
>> > > >
>> > > >> This adds the devicetree binding for the Tegra 2 NAND flash
>> > > >> controller.
>> > > >>
>> > > >> Signed-off-by: Lucas Stach <dev@lynxeye.de>
>> > > >> Signed-off-by: Stefan Agner <stefan@agner.ch>
>> > > >> ---
>> > > >>  .../bindings/mtd/nvidia-tegra20-nand.txt      | 64 +++++++++++++++++++
>> > > >>  1 file changed, 64 insertions(+)
>> > > >>  create mode 100644 Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> > > >>
>> > > >> diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> > > >> new file mode 100644
>> > > >> index 000000000000..5cd984ef046b
>> > > >> --- /dev/null
>> > > >> +++ b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> > > >> @@ -0,0 +1,64 @@
>> > > >> +NVIDIA Tegra NAND Flash controller
>> > > >> +
>> > > >> +Required properties:
>> > > >> +- compatible: Must be one of:
>> > > >> +  - "nvidia,tegra20-nand"
>> > > >
>> > > > As discussed previously, I prefer "nvidia,tegra20-nand-controller" or
>> > > > "nvidia,tegra20-nfc".
>> > > >
>> > > >> +- reg: MMIO address range
>> > > >> +- interrupts: interrupt output of the NFC controller
>> > > >> +- clocks: Must contain an entry for each entry in clock-names.
>> > > >> +  See ../clocks/clock-bindings.txt for details.
>> > > >> +- clock-names: Must include the following entries:
>> > > >> +  - nand
>> > > >> +- resets: Must contain an entry for each entry in reset-names.
>> > > >> +  See ../reset/reset.txt for details.
>> > > >> +- reset-names: Must include the following entries:
>> > > >> +  - nand
>> > > >> +
>> > > >> +Optional children nodes:
>> > > >> +Individual NAND chips are children of the NAND controller node. Currently
>> > > >> +only one NAND chip supported.
>> > > >> +
>> > > >> +Required children node properties:
>> > > >> +- reg: An integer ranging from 1 to 6 representing the CS line to use.
>> > > >> +
>> > > >> +Optional children node properties:
>> > > >> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
>> > > >> +		 "hw" is supported.
>> > > >> +- nand-ecc-algo: string, algorithm of NAND ECC.
>> > > >> +		 Supported values with "hw" ECC mode are: "rs", "bch".
>> > > >> +- nand-bus-width : See nand.txt
>> > > >> +- nand-on-flash-bbt: See nand.txt
>> > > >> +- nand-ecc-strength: integer representing the number of bits to correct
>> > > >> +		     per ECC step (always 512). Supported strength using HW ECC
>> > > >> +		     modes are:
>> > > >> +		     - RS: 4, 6, 8
>> > > >> +		     - BCH: 4, 8, 14, 16
>> > > >> +- nand-ecc-maximize: See nand.txt
>> > > >> +- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
>> > > >> +		       are choosen.
>> > > >> +- wp-gpios: GPIO specifier for the write protect pin.
>> > > >> +
>> > > >> +Optional child node of NAND chip nodes:
>> > > >> +Partitions: see partition.txt
>> > > >> +
>> > > >> +  Example:
>> > > >> +	nand@70008000 {
>> > > >
>> > > > 	nand-controller@70008000 {
>> > > >
>> > > >> +		compatible = "nvidia,tegra20-nand";
>> > > >
>> > > > 		compatible = "nvidia,tegra20-nand-controller";
>> > > >
>> > > > or
>> > > >
>> > > > 		compatible = "nvidia,tegra20-nfc";
>> > > >
>> > >
>> > > Maybe it's just me, but when I'm reading "nfc", my first association is the
>> > > "Near Field Communication". Probably an explicit
>> > > "nvidia,tegra20-nand-controller" variant is more preferable.
>>
>> I also prefer nvidia,tegra20-nand-controller.
>>
>> >
>> > We don't really use a -controller suffix for any of the other
>> > controllers because it is kind of implied. "nfc" is also not something
>> > that is ever referred to in the technical documentation.
>> >
>> > "nvidia,tegra20-nand" would be most consistent with all the rest of
>> > Tegra (c.f. "nvidia,tegra*-ahci", "nvidia,tegra*-pci",
>> > "nvidia,tegra*-hda", "nvidia,tegra*-gmi", ...).
>>
>> People get confused about what this node represents when you just have
>> "nvidia,tegra20-nand", and then you start seeing NAND related props or
>> partition nodes being defined under the NAND controller node.
>> I really prefer to have the "-controller" prefix here to avoid such
>> confusions.
> 
> Hmm... odd. I mean, the node is already called nand-controller@...,
> which makes it pretty obvious to me that this represents a controller
> rather than a NAND chip. Also, the placement of this in the DT hierarchy
> should make it pretty obvious that it is a controller since you can't
> just put a NAND chip directly on the CPU's address bus.
> 
> In addition I think the nvidia,tegra* part already pretty strongly
> suggests that this is part of an SoC, so further implies "controller".

The reference manual states:
"16.0 NAND FLASH CONTROLLER

The NAND flash controller allows Tegra 2 Processor to access NAND flash
memories for mass storage."

So I guess "nvidia,tegra20-nand-flash-controller" would be most
explicit. But the manual also has "GPIO controller" and we use
"nvidia,tegra20-gpio" as compatible string.

I dislike nfc since it is an increasingly less known abbreviation and
not used in the reference manual at all.

"nvidia,tegra20-nand" or "nvidia,tegra20-nand-flash-controller" is fine
for me...

--
Stefan

  reply	other threads:[~2018-06-06 12:14 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-31 22:16 [PATCH v3 0/6] mtd: rawnand: add NVIDIA Tegra NAND flash support Stefan Agner
2018-05-31 22:16 ` [PATCH v3 1/6] mtd: rawnand: add Reed-Solomon error correction algorithm Stefan Agner
2018-06-01  7:26   ` Boris Brezillon
2018-06-01  9:25     ` Boris Brezillon
2018-06-01 13:34       ` Stefan Agner
2018-06-01 13:43         ` Boris Brezillon
2018-05-31 22:16 ` [PATCH v3 2/6] mtd: rawnand: add an option to specify NAND chip as a boot device Stefan Agner
2018-06-01  7:26   ` Boris Brezillon
2018-06-05 20:11   ` Rob Herring
2018-06-06  7:28     ` Boris Brezillon
2018-05-31 22:16 ` [PATCH v3 3/6] mtd: rawnand: tegra: add devicetree binding Stefan Agner
2018-06-01  7:30   ` Boris Brezillon
2018-06-05 20:19     ` Dmitry Osipenko
2018-06-06 10:39       ` Thierry Reding
2018-06-06 10:45         ` Boris Brezillon
2018-06-06 11:07           ` Thierry Reding
2018-06-06 12:14             ` Stefan Agner [this message]
2018-06-06 12:31               ` Boris Brezillon
2018-06-05 20:13   ` Rob Herring
2018-05-31 22:16 ` [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver Stefan Agner
2018-06-01  9:20   ` Dmitry Osipenko
2018-06-08 21:51     ` Stefan Agner
2018-06-09  5:52       ` Boris Brezillon
2018-06-09  6:23         ` Stefan Agner
2018-06-09  6:41           ` Boris Brezillon
2018-06-09  6:46             ` Boris Brezillon
2018-06-09  6:55               ` Boris Brezillon
2018-06-09  6:51             ` Stefan Agner
2018-06-09 12:21       ` Dmitry Osipenko
2018-06-10 11:09         ` Stefan Agner
2018-06-10 15:00           ` Dmitry Osipenko
2018-06-10 15:32             ` Boris Brezillon
2018-06-11 11:45               ` Dmitry Osipenko
2018-06-11 11:50                 ` Boris Brezillon
2018-06-11 13:10                   ` Dmitry Osipenko
2018-06-04 17:16   ` Randolph Maaßen
2018-06-04 20:56     ` Stefan Agner
2018-06-09  5:55   ` Boris Brezillon
2018-06-09  7:18   ` Boris Brezillon
2018-05-31 22:16 ` [PATCH v3 5/6] ARM: dts: tegra: add Tegra20 NAND flash controller node Stefan Agner
2018-05-31 22:16 ` [PATCH v3 6/6] ARM: dts: tegra: enable NAND flash on Colibri T20 Stefan Agner

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=c687fc59e2662d07568f94efb55bc250@agner.ch \
    --to=stefan@agner.ch \
    --cc=benjamin.lindqvist@endian.se \
    --cc=boris.brezillon@bootlin.com \
    --cc=computersforpeace@gmail.com \
    --cc=dev@lynxeye.de \
    --cc=devicetree@vger.kernel.org \
    --cc=digetx@gmail.com \
    --cc=dwmw2@infradead.org \
    --cc=jonathanh@nvidia.com \
    --cc=krzk@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mtd@lists.infradead.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=marcel@ziswiler.com \
    --cc=marek.vasut@gmail.com \
    --cc=mark.rutland@arm.com \
    --cc=miquel.raynal@bootlin.com \
    --cc=mirza.krak@gmail.com \
    --cc=pdeschrijver@nvidia.com \
    --cc=pgaikwad@nvidia.com \
    --cc=richard@nod.at \
    --cc=robh+dt@kernel.org \
    --cc=thierry.reding@gmail.com \
    --subject='Re: [PATCH v3 3/6] mtd: rawnand: tegra: add devicetree binding' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).