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From: Christophe Leroy <christophe.leroy@c-s.fr>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Paul Mackerras <paulus@samba.org>,
	Michael Ellerman <mpe@ellerman.id.au>
Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH v6 07/20] powerpc/8xx: Use patch_site for memory setup patching
Date: Fri, 19 Oct 2018 06:55:06 +0000 (UTC)	[thread overview]
Message-ID: <c75a3503a979bbb1873bfb2749e03cfc040052ae.1539931702.git.christophe.leroy@c-s.fr> (raw)
In-Reply-To: <cover.1539931702.git.christophe.leroy@c-s.fr>

The 8xx TLB miss routines are patched at startup at several places.

This patch uses the new patch_site functionality in order
to get a better code readability and avoid a label mess when
dumping the code with 'objdump -d'

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
 arch/powerpc/include/asm/nohash/32/mmu-8xx.h |  5 +++++
 arch/powerpc/kernel/head_8xx.S               | 19 +++++++++++--------
 arch/powerpc/mm/8xx_mmu.c                    | 23 +++++++----------------
 3 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
index 193f53116c7a..3a15d6647d47 100644
--- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
@@ -229,6 +229,11 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
 	BUG();
 }
 
+/* patch sites */
+extern s32 patch__itlbmiss_linmem_top;
+extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp;
+extern s32 patch__fixupdar_linmem_top;
+
 #endif /* !__ASSEMBLY__ */
 
 #if defined(CONFIG_PPC_4K_PAGES)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 12c92a483fb1..0425571a533d 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -31,6 +31,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/ptrace.h>
 #include <asm/export.h>
+#include <asm/code-patching-asm.h>
 
 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
@@ -318,8 +319,8 @@ InstructionTLBMiss:
 	cmpli	cr0, r11, PAGE_OFFSET@h
 #ifndef CONFIG_PIN_TLB_TEXT
 	/* It is assumed that kernel code fits into the first 8M page */
-_ENTRY(ITLBMiss_cmp)
-	cmpli	cr7, r11, (PAGE_OFFSET + 0x0800000)@h
+0:	cmpli	cr7, r11, (PAGE_OFFSET + 0x0800000)@h
+	patch_site	0b, patch__itlbmiss_linmem_top
 #endif
 #endif
 #endif
@@ -436,11 +437,11 @@ DataStoreTLBMiss:
 #ifndef CONFIG_PIN_TLB_IMMR
 	cmpli	cr0, r11, VIRT_IMMR_BASE@h
 #endif
-_ENTRY(DTLBMiss_cmp)
-	cmpli	cr7, r11, (PAGE_OFFSET + 0x1800000)@h
+0:	cmpli	cr7, r11, (PAGE_OFFSET + 0x1800000)@h
+	patch_site	0b, patch__dtlbmiss_linmem_top
 #ifndef CONFIG_PIN_TLB_IMMR
-_ENTRY(DTLBMiss_jmp)
-	beq-	DTLBMissIMMR
+0:	beq-	DTLBMissIMMR
+	patch_site	0b, patch__dtlbmiss_immr_jmp
 #endif
 	blt	cr7, DTLBMissLinear
 	lis	r11, (swapper_pg_dir-PAGE_OFFSET)@ha
@@ -714,8 +715,10 @@ FixupDAR:/* Entry point for dcbx workaround. */
 	mfspr	r11, SPRN_M_TW	/* Get level 1 table */
 	blt+	3f
 	rlwinm	r11, r10, 16, 0xfff8
-_ENTRY(FixupDAR_cmp)
-	cmpli	cr7, r11, (PAGE_OFFSET + 0x1800000)@h
+
+0:	cmpli	cr7, r11, (PAGE_OFFSET + 0x1800000)@h
+	patch_site	0b, patch__fixupdar_linmem_top
+
 	/* create physical page address from effective address */
 	tophys(r11, r10)
 	blt-	cr7, 201f
diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c
index fee599cf3bc3..d39f3af03221 100644
--- a/arch/powerpc/mm/8xx_mmu.c
+++ b/arch/powerpc/mm/8xx_mmu.c
@@ -97,22 +97,13 @@ static void __init mmu_mapin_immr(void)
 		map_kernel_page(v + offset, p + offset, PAGE_KERNEL_NCG);
 }
 
-/* Address of instructions to patch */
-#ifndef CONFIG_PIN_TLB_IMMR
-extern unsigned int DTLBMiss_jmp;
-#endif
-extern unsigned int DTLBMiss_cmp, FixupDAR_cmp;
-#ifndef CONFIG_PIN_TLB_TEXT
-extern unsigned int ITLBMiss_cmp;
-#endif
-
-static void __init mmu_patch_cmp_limit(unsigned int *addr, unsigned long mapped)
+static void __init mmu_patch_cmp_limit(s32 *site, unsigned long mapped)
 {
-	unsigned int instr = *addr;
+	unsigned int instr = *(unsigned int *)site_addr(site);
 
 	instr &= 0xffff0000;
 	instr |= (unsigned long)__va(mapped) >> 16;
-	patch_instruction(addr, instr);
+	patch_instruction_site(site, instr);
 }
 
 unsigned long __init mmu_mapin_ram(unsigned long top)
@@ -123,17 +114,17 @@ unsigned long __init mmu_mapin_ram(unsigned long top)
 		mapped = 0;
 		mmu_mapin_immr();
 #ifndef CONFIG_PIN_TLB_IMMR
-		patch_instruction(&DTLBMiss_jmp, PPC_INST_NOP);
+		patch_instruction_site(&patch__dtlbmiss_immr_jmp, PPC_INST_NOP);
 #endif
 #ifndef CONFIG_PIN_TLB_TEXT
-		mmu_patch_cmp_limit(&ITLBMiss_cmp, 0);
+		mmu_patch_cmp_limit(&patch__itlbmiss_linmem_top, 0);
 #endif
 	} else {
 		mapped = top & ~(LARGE_PAGE_SIZE_8M - 1);
 	}
 
-	mmu_patch_cmp_limit(&DTLBMiss_cmp, mapped);
-	mmu_patch_cmp_limit(&FixupDAR_cmp, mapped);
+	mmu_patch_cmp_limit(&patch__dtlbmiss_linmem_top, mapped);
+	mmu_patch_cmp_limit(&patch__fixupdar_linmem_top, mapped);
 
 	/* If the size of RAM is not an exact power of two, we may not
 	 * have covered RAM in its entirety with 8 MiB
-- 
2.13.3


  parent reply	other threads:[~2018-10-19  6:55 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-19  6:54 [PATCH v6 00/20] Implement use of HW assistance on TLB table walk on 8xx Christophe Leroy
2018-10-19  6:54 ` [PATCH v6 01/20] Revert "powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED for CONFIG_SWAP" Christophe Leroy
2018-10-31  5:42   ` [v6, " Michael Ellerman
2018-10-19  6:54 ` [PATCH v6 02/20] powerpc/mm: Move pte_fragment_alloc() to a common location Christophe Leroy
2018-10-19  6:54 ` [PATCH v6 03/20] powerpc/mm: Avoid useless lock with single page fragments Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 04/20] powerpc/mm: move platform specific mmu-xxx.h in platform directories Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 05/20] powerpc/mm: Move pgtable_t into platform headers Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 06/20] powerpc/code-patching: add a helper to get the address of a patch_site Christophe Leroy
2018-10-31  5:42   ` [v6, " Michael Ellerman
2018-10-19  6:55 ` Christophe Leroy [this message]
2018-10-31  5:42   ` [v6,07/20] powerpc/8xx: Use patch_site for memory setup patching Michael Ellerman
2018-10-19  6:55 ` [PATCH v6 08/20] powerpc/8xx: Use patch_site for perf counters setup Christophe Leroy
2018-10-31  5:42   ` [v6,08/20] " Michael Ellerman
2018-10-19  6:55 ` [PATCH v6 09/20] powerpc/8xx: Move SW perf counters in first 32kb of memory Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 10/20] powerpc/8xx: Temporarily disable 16k pages and 512k hugepages Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 11/20] powerpc/mm: Use hardware assistance in TLB handlers on the 8xx Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 12/20] powerpc/mm: Enable 512k hugepage support with HW assistance " Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 13/20] powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 14/20] powerpc/8xx: regroup TLB handler routines Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 15/20] powerpc/mm: don't use pte_alloc_one_kernel() before slab is available Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 16/20] powerpc/mm: inline pte_alloc_one() and pte_alloc_one_kernel() in PPC32 Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 17/20] powerpc/book3s32: Remove CONFIG_BOOKE dependent code Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 18/20] powerpc/mm: Extend pte_fragment functionality to nohash/32 Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 19/20] powerpc/8xx: Remove PTE_ATOMIC_UPDATES Christophe Leroy
2018-10-19  6:55 ` [PATCH v6 20/20] powerpc/mm: reintroduce 16K pages with HW assistance on 8xx Christophe Leroy

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