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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Tom Joseph <tjoseph@cadence.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Marek Vasut <marek.vasut+renesas@gmail.com>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	Shawn Lin <shawn.lin@rock-chips.com>,
	Heiko Stuebner <heiko@sntech.de>,
	Jonathan Corbet <corbet@lwn.net>, Arnd Bergmann <arnd@arndb.de>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	<linux-pci@vger.kernel.org>, <linux-doc@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-rockchip@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Lokesh Vutla <lokeshvutla@ti.com>
Subject: Re: [PATCH v8 6/8] PCI: cadence: Add support to configure virtual functions
Date: Wed, 18 Aug 2021 19:25:09 +0530	[thread overview]
Message-ID: <ce380e6f-d10a-4db2-9bde-82615cfbe4db@ti.com> (raw)
In-Reply-To: <20210817153852.GA3016660@bjorn-Precision-5520>

Hi Bjorn,

On 17/08/21 9:08 pm, Bjorn Helgaas wrote:
> On Wed, Aug 11, 2021 at 12:16:54PM +0530, Kishon Vijay Abraham I wrote:
>> Now that support for SR-IOV is added in PCIe endpoint core, add support
>> to configure virtual functions in the Cadence PCIe EP driver.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>>  .../pci/controller/cadence/pcie-cadence-ep.c  | 136 +++++++++++++++---
>>  drivers/pci/controller/cadence/pcie-cadence.h |   9 ++
>>  2 files changed, 125 insertions(+), 20 deletions(-)
> 
>> @@ -92,21 +118,29 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
>>  
>>  	addr0 = lower_32_bits(bar_phys);
>>  	addr1 = upper_32_bits(bar_phys);
>> -	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
>> -			 addr0);
>> -	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
>> -			 addr1);
>>  
>>  	reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn);
>> +	if (vfn == 1)
>> +		reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn);
> 
> Seems sort of weird to compute "reg", then sometimes overwrite it, as
> opposed to:
> 
>   if (vfn == 1)
>     reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn);
>   else
>     reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn);

I tried to write it without "else". But I can change it back.
> 
> Also slightly weird that "vfn" is basically used as a boolean, but
> it's actually a u8 virtual function number.  I guess VF 1 is special
> and not like the other VFs?

VF1 is special in that it's enough for configuring the SR-IOV capability
but below the "vfn" is used for configuring inbound window.

Thanks
Kishon
> 
>>  	b = (bar < BAR_4) ? bar : bar - BAR_4;
>>  
>> -	cfg = cdns_pcie_readl(pcie, reg);
>> -	cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
>> -		 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
>> -	cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
>> -		CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
>> -	cdns_pcie_writel(pcie, reg, cfg);
>> +	if (vfn == 0 || vfn == 1) {
>> +		cfg = cdns_pcie_readl(pcie, reg);
>> +		cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
>> +			 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
>> +		cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
>> +			CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
>> +		cdns_pcie_writel(pcie, reg, cfg);
>> +	}
>>  
>> +	fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn);
>> +	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
>> +			 addr0);
>> +	cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
>> +			 addr1);
>> +
>> +	if (vfn > 0)
>> +		epf = &epf->epf[vfn - 1];
>>  	epf->epf_bar[bar] = epf_bar;
>>  
>>  	return 0;
>> @@ -122,18 +156,25 @@ static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn,
>>  	u32 reg, cfg, b, ctrl;
>>  
>>  	reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn);
>> +	if (vfn == 1)
>> +		reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn);
> 
> Similar recomputation of "reg".
> 
>>  	b = (bar < BAR_4) ? bar : bar - BAR_4;
>>  
>> -	ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
>> -	cfg = cdns_pcie_readl(pcie, reg);
>> -	cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
>> -		 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
>> -	cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
>> -	cdns_pcie_writel(pcie, reg, cfg);
>> +	if (vfn == 0 || vfn == 1) {
>> +		ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
>> +		cfg = cdns_pcie_readl(pcie, reg);
>> +		cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
>> +			 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
>> +		cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
>> +		cdns_pcie_writel(pcie, reg, cfg);
>> +	}

  reply	other threads:[~2021-08-18 13:56 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-11  6:46 [PATCH v8 0/8] Add SR-IOV support in PCIe Endpoint Core Kishon Vijay Abraham I
2021-08-11  6:46 ` [PATCH v8 1/8] dt-bindings: PCI: pci-ep: Add binding to specify virtual function Kishon Vijay Abraham I
2021-08-11  6:46 ` [PATCH v8 2/8] PCI: endpoint: Add support to add virtual function in endpoint core Kishon Vijay Abraham I
2021-08-11  6:46 ` [PATCH v8 3/8] PCI: endpoint: Add support to link a physical function to a virtual function Kishon Vijay Abraham I
2021-08-11  6:46 ` [PATCH v8 4/8] PCI: endpoint: Add virtual function number in pci_epc ops Kishon Vijay Abraham I
2021-08-11  6:46 ` [PATCH v8 5/8] PCI: cadence: Simplify code to get register base address for configuring BAR Kishon Vijay Abraham I
2021-08-17 15:24   ` Bjorn Helgaas
2021-08-11  6:46 ` [PATCH v8 6/8] PCI: cadence: Add support to configure virtual functions Kishon Vijay Abraham I
2021-08-17 15:38   ` Bjorn Helgaas
2021-08-18 13:55     ` Kishon Vijay Abraham I [this message]
2021-08-11  6:46 ` [PATCH v8 7/8] misc: pci_endpoint_test: Populate sriov_configure ops to configure SR-IOV device Kishon Vijay Abraham I
2021-08-11  6:46 ` [PATCH v8 8/8] Documentation: PCI: endpoint/pci-endpoint-cfs: Guide to use SR-IOV Kishon Vijay Abraham I
2021-08-16 17:01 ` [PATCH v8 0/8] Add SR-IOV support in PCIe Endpoint Core Lorenzo Pieralisi

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