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* [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A
@ 2015-01-22  7:30 micky_ching
  2015-01-22  7:30 ` [RESEND PATCH v2 1/9] mfd: rtsx: replace TAB by SPC after #define micky_ching
                   ` (8 more replies)
  0 siblings, 9 replies; 19+ messages in thread
From: micky_ching @ 2015-01-22  7:30 UTC (permalink / raw)
  To: sameo, lee.jones
  Cc: devel, linux-kernel, gregkh, rogerable, wei_wang, Micky Ching

From: Micky Ching <micky_ching@realsil.com.cn>

resend:
- add lee jones ack for some patch.
v2:
- remove debug info when access failed.
- using macro list for phy register init.
- rename function for multi chip prefix with rtsx_base_
- save pcie_cap offset when init chip, not calling pci_find_capacity()
  every time.
- add pcr->ops: write_phy/read_phy for special chip.

This patchset including re-format some coding-style and add two new chip
rts524A and rts525A.


Micky Ching (9):
  mfd: rtsx: replace TAB by SPC after #define
  mfd: rtsx: place register address and values togather
  mfd: rtsx: update PETXCFG address
  mfd: rtsx: update driving settings
  mfd: rtsx: update phy register
  mfd: rtsx: remove LCTLR defination
  mfd: rtsx: add support for rts524A
  mfd: rtsx: add support for rts525A
  mfd: rtsx: using pcr_dbg replace dev_dbg

 drivers/mfd/Makefile         |    2 +-
 drivers/mfd/rtl8411.c        |   11 +-
 drivers/mfd/rts5209.c        |    4 +-
 drivers/mfd/rts5227.c        |   12 +-
 drivers/mfd/rts5229.c        |    4 +-
 drivers/mfd/rts5249.c        |  368 +++++++++++---
 drivers/mfd/rtsx_gops.c      |   37 --
 drivers/mfd/rtsx_pcr.c       |  109 +++--
 drivers/mfd/rtsx_pcr.h       |    8 +
 include/linux/mfd/rtsx_pci.h | 1109 ++++++++++++++++++++++--------------------
 10 files changed, 965 insertions(+), 699 deletions(-)
 delete mode 100644 drivers/mfd/rtsx_gops.c

-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [RESEND PATCH v2 1/9] mfd: rtsx: replace TAB by SPC after #define
  2015-01-22  7:30 [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A micky_ching
@ 2015-01-22  7:30 ` micky_ching
  2015-01-22  7:30 ` [RESEND PATCH v2 2/9] mfd: rtsx: place register address and values togather micky_ching
                   ` (7 subsequent siblings)
  8 siblings, 0 replies; 19+ messages in thread
From: micky_ching @ 2015-01-22  7:30 UTC (permalink / raw)
  To: sameo, lee.jones
  Cc: devel, linux-kernel, gregkh, rogerable, wei_wang, Micky Ching

From: Micky Ching <micky_ching@realsil.com.cn>

Re-format coding-style, using uniform SPC after "#define" keyword
instead of mixing using TAB and SPC.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
 include/linux/mfd/rtsx_pci.h | 254 +++++++++++++++++++++----------------------
 1 file changed, 127 insertions(+), 127 deletions(-)

diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 0c12628..a9c2a14 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -175,9 +175,9 @@
 /* CARD_SHARE_MODE */
 #define CARD_SHARE_MASK			0x0F
 #define CARD_SHARE_MULTI_LUN		0x00
-#define	CARD_SHARE_NORMAL		0x00
-#define	CARD_SHARE_48_SD		0x04
-#define	CARD_SHARE_48_MS		0x08
+#define CARD_SHARE_NORMAL		0x00
+#define CARD_SHARE_48_SD		0x04
+#define CARD_SHARE_48_MS		0x08
 /* CARD_SHARE_MODE for barossa */
 #define CARD_SHARE_BAROSSA_SD		0x01
 #define CARD_SHARE_BAROSSA_MS		0x02
@@ -249,76 +249,76 @@
 #define CD_AUTO_DISABLE			0x40
 
 /* SD_STAT1 */
-#define	SD_CRC7_ERR			0x80
-#define	SD_CRC16_ERR			0x40
-#define	SD_CRC_WRITE_ERR		0x20
-#define	SD_CRC_WRITE_ERR_MASK		0x1C
-#define	GET_CRC_TIME_OUT		0x02
-#define	SD_TUNING_COMPARE_ERR		0x01
+#define SD_CRC7_ERR			0x80
+#define SD_CRC16_ERR			0x40
+#define SD_CRC_WRITE_ERR		0x20
+#define SD_CRC_WRITE_ERR_MASK		0x1C
+#define GET_CRC_TIME_OUT		0x02
+#define SD_TUNING_COMPARE_ERR		0x01
 
 /* SD_STAT2 */
-#define	SD_RSP_80CLK_TIMEOUT		0x01
+#define SD_RSP_80CLK_TIMEOUT		0x01
 
 /* SD_BUS_STAT */
-#define	SD_CLK_TOGGLE_EN		0x80
-#define	SD_CLK_FORCE_STOP	        0x40
-#define	SD_DAT3_STATUS		        0x10
-#define	SD_DAT2_STATUS		        0x08
-#define	SD_DAT1_STATUS		        0x04
-#define	SD_DAT0_STATUS		        0x02
-#define	SD_CMD_STATUS			0x01
+#define SD_CLK_TOGGLE_EN		0x80
+#define SD_CLK_FORCE_STOP	        0x40
+#define SD_DAT3_STATUS		        0x10
+#define SD_DAT2_STATUS		        0x08
+#define SD_DAT1_STATUS		        0x04
+#define SD_DAT0_STATUS		        0x02
+#define SD_CMD_STATUS			0x01
 
 /* SD_PAD_CTL */
-#define	SD_IO_USING_1V8		        0x80
-#define	SD_IO_USING_3V3		        0x7F
-#define	TYPE_A_DRIVING		        0x00
-#define	TYPE_B_DRIVING			0x01
-#define	TYPE_C_DRIVING			0x02
-#define	TYPE_D_DRIVING		        0x03
+#define SD_IO_USING_1V8		        0x80
+#define SD_IO_USING_3V3		        0x7F
+#define TYPE_A_DRIVING		        0x00
+#define TYPE_B_DRIVING			0x01
+#define TYPE_C_DRIVING			0x02
+#define TYPE_D_DRIVING		        0x03
 
 /* SD_SAMPLE_POINT_CTL */
-#define	DDR_FIX_RX_DAT			0x00
-#define	DDR_VAR_RX_DAT			0x80
-#define	DDR_FIX_RX_DAT_EDGE		0x00
-#define	DDR_FIX_RX_DAT_14_DELAY		0x40
-#define	DDR_FIX_RX_CMD			0x00
-#define	DDR_VAR_RX_CMD			0x20
-#define	DDR_FIX_RX_CMD_POS_EDGE		0x00
-#define	DDR_FIX_RX_CMD_14_DELAY		0x10
-#define	SD20_RX_POS_EDGE		0x00
-#define	SD20_RX_14_DELAY		0x08
+#define DDR_FIX_RX_DAT			0x00
+#define DDR_VAR_RX_DAT			0x80
+#define DDR_FIX_RX_DAT_EDGE		0x00
+#define DDR_FIX_RX_DAT_14_DELAY		0x40
+#define DDR_FIX_RX_CMD			0x00
+#define DDR_VAR_RX_CMD			0x20
+#define DDR_FIX_RX_CMD_POS_EDGE		0x00
+#define DDR_FIX_RX_CMD_14_DELAY		0x10
+#define SD20_RX_POS_EDGE		0x00
+#define SD20_RX_14_DELAY		0x08
 #define SD20_RX_SEL_MASK		0x08
 
 /* SD_PUSH_POINT_CTL */
-#define	DDR_FIX_TX_CMD_DAT		0x00
-#define	DDR_VAR_TX_CMD_DAT		0x80
-#define	DDR_FIX_TX_DAT_14_TSU		0x00
-#define	DDR_FIX_TX_DAT_12_TSU		0x40
-#define	DDR_FIX_TX_CMD_NEG_EDGE		0x00
-#define	DDR_FIX_TX_CMD_14_AHEAD		0x20
-#define	SD20_TX_NEG_EDGE		0x00
-#define	SD20_TX_14_AHEAD		0x10
+#define DDR_FIX_TX_CMD_DAT		0x00
+#define DDR_VAR_TX_CMD_DAT		0x80
+#define DDR_FIX_TX_DAT_14_TSU		0x00
+#define DDR_FIX_TX_DAT_12_TSU		0x40
+#define DDR_FIX_TX_CMD_NEG_EDGE		0x00
+#define DDR_FIX_TX_CMD_14_AHEAD		0x20
+#define SD20_TX_NEG_EDGE		0x00
+#define SD20_TX_14_AHEAD		0x10
 #define SD20_TX_SEL_MASK		0x10
-#define	DDR_VAR_SDCLK_POL_SWAP		0x01
+#define DDR_VAR_SDCLK_POL_SWAP		0x01
 
 /* SD_TRANSFER */
-#define	SD_TRANSFER_START		0x80
-#define	SD_TRANSFER_END			0x40
+#define SD_TRANSFER_START		0x80
+#define SD_TRANSFER_END			0x40
 #define SD_STAT_IDLE			0x20
-#define	SD_TRANSFER_ERR			0x10
+#define SD_TRANSFER_ERR			0x10
 /* SD Transfer Mode definition */
-#define	SD_TM_NORMAL_WRITE		0x00
-#define	SD_TM_AUTO_WRITE_3		0x01
-#define	SD_TM_AUTO_WRITE_4		0x02
-#define	SD_TM_AUTO_READ_3		0x05
-#define	SD_TM_AUTO_READ_4		0x06
-#define	SD_TM_CMD_RSP			0x08
-#define	SD_TM_AUTO_WRITE_1		0x09
-#define	SD_TM_AUTO_WRITE_2		0x0A
-#define	SD_TM_NORMAL_READ		0x0C
-#define	SD_TM_AUTO_READ_1		0x0D
-#define	SD_TM_AUTO_READ_2		0x0E
-#define	SD_TM_AUTO_TUNING		0x0F
+#define SD_TM_NORMAL_WRITE		0x00
+#define SD_TM_AUTO_WRITE_3		0x01
+#define SD_TM_AUTO_WRITE_4		0x02
+#define SD_TM_AUTO_READ_3		0x05
+#define SD_TM_AUTO_READ_4		0x06
+#define SD_TM_CMD_RSP			0x08
+#define SD_TM_AUTO_WRITE_1		0x09
+#define SD_TM_AUTO_WRITE_2		0x0A
+#define SD_TM_NORMAL_READ		0x0C
+#define SD_TM_AUTO_READ_1		0x0D
+#define SD_TM_AUTO_READ_2		0x0E
+#define SD_TM_AUTO_TUNING		0x0F
 
 /* SD_VPTX_CTL / SD_VPRX_CTL */
 #define PHASE_CHANGE			0x80
@@ -332,15 +332,15 @@
 
 /* SD Configure 1 Register */
 #define SD_CLK_DIVIDE_0			0x00
-#define	SD_CLK_DIVIDE_256		0xC0
-#define	SD_CLK_DIVIDE_128		0x80
-#define	SD_BUS_WIDTH_1BIT		0x00
-#define	SD_BUS_WIDTH_4BIT		0x01
-#define	SD_BUS_WIDTH_8BIT		0x02
-#define	SD_ASYNC_FIFO_NOT_RST		0x10
-#define	SD_20_MODE			0x00
-#define	SD_DDR_MODE			0x04
-#define	SD_30_MODE			0x08
+#define SD_CLK_DIVIDE_256		0xC0
+#define SD_CLK_DIVIDE_128		0x80
+#define SD_BUS_WIDTH_1BIT		0x00
+#define SD_BUS_WIDTH_4BIT		0x01
+#define SD_BUS_WIDTH_8BIT		0x02
+#define SD_ASYNC_FIFO_NOT_RST		0x10
+#define SD_20_MODE			0x00
+#define SD_DDR_MODE			0x04
+#define SD_30_MODE			0x08
 
 #define SD_CLK_DIVIDE_MASK		0xC0
 
@@ -415,71 +415,71 @@
 #define CLK_DIV_8			0x04
 
 /* MS_CFG */
-#define	SAMPLE_TIME_RISING		0x00
-#define	SAMPLE_TIME_FALLING		0x80
-#define	PUSH_TIME_DEFAULT		0x00
-#define	PUSH_TIME_ODD			0x40
-#define	NO_EXTEND_TOGGLE		0x00
-#define	EXTEND_TOGGLE_CHK		0x20
-#define	MS_BUS_WIDTH_1			0x00
-#define	MS_BUS_WIDTH_4			0x10
-#define	MS_BUS_WIDTH_8			0x18
-#define	MS_2K_SECTOR_MODE		0x04
-#define	MS_512_SECTOR_MODE		0x00
-#define	MS_TOGGLE_TIMEOUT_EN		0x00
-#define	MS_TOGGLE_TIMEOUT_DISEN		0x01
+#define SAMPLE_TIME_RISING		0x00
+#define SAMPLE_TIME_FALLING		0x80
+#define PUSH_TIME_DEFAULT		0x00
+#define PUSH_TIME_ODD			0x40
+#define NO_EXTEND_TOGGLE		0x00
+#define EXTEND_TOGGLE_CHK		0x20
+#define MS_BUS_WIDTH_1			0x00
+#define MS_BUS_WIDTH_4			0x10
+#define MS_BUS_WIDTH_8			0x18
+#define MS_2K_SECTOR_MODE		0x04
+#define MS_512_SECTOR_MODE		0x00
+#define MS_TOGGLE_TIMEOUT_EN		0x00
+#define MS_TOGGLE_TIMEOUT_DISEN		0x01
 #define MS_NO_CHECK_INT			0x02
 
 /* MS_TRANS_CFG */
-#define	WAIT_INT			0x80
-#define	NO_WAIT_INT			0x00
-#define	NO_AUTO_READ_INT_REG		0x00
-#define	AUTO_READ_INT_REG		0x40
-#define	MS_CRC16_ERR			0x20
-#define	MS_RDY_TIMEOUT			0x10
-#define	MS_INT_CMDNK			0x08
-#define	MS_INT_BREQ			0x04
-#define	MS_INT_ERR			0x02
-#define	MS_INT_CED			0x01
+#define WAIT_INT			0x80
+#define NO_WAIT_INT			0x00
+#define NO_AUTO_READ_INT_REG		0x00
+#define AUTO_READ_INT_REG		0x40
+#define MS_CRC16_ERR			0x20
+#define MS_RDY_TIMEOUT			0x10
+#define MS_INT_CMDNK			0x08
+#define MS_INT_BREQ			0x04
+#define MS_INT_ERR			0x02
+#define MS_INT_CED			0x01
 
 /* MS_TRANSFER */
-#define	MS_TRANSFER_START		0x80
-#define	MS_TRANSFER_END			0x40
-#define	MS_TRANSFER_ERR			0x20
-#define	MS_BS_STATE			0x10
-#define	MS_TM_READ_BYTES		0x00
-#define	MS_TM_NORMAL_READ		0x01
-#define	MS_TM_WRITE_BYTES		0x04
-#define	MS_TM_NORMAL_WRITE		0x05
-#define	MS_TM_AUTO_READ			0x08
-#define	MS_TM_AUTO_WRITE		0x0C
+#define MS_TRANSFER_START		0x80
+#define MS_TRANSFER_END			0x40
+#define MS_TRANSFER_ERR			0x20
+#define MS_BS_STATE			0x10
+#define MS_TM_READ_BYTES		0x00
+#define MS_TM_NORMAL_READ		0x01
+#define MS_TM_WRITE_BYTES		0x04
+#define MS_TM_NORMAL_WRITE		0x05
+#define MS_TM_AUTO_READ			0x08
+#define MS_TM_AUTO_WRITE		0x0C
 
 /* SD Configure 2 Register */
-#define	SD_CALCULATE_CRC7		0x00
-#define	SD_NO_CALCULATE_CRC7		0x80
-#define	SD_CHECK_CRC16			0x00
-#define	SD_NO_CHECK_CRC16		0x40
+#define SD_CALCULATE_CRC7		0x00
+#define SD_NO_CALCULATE_CRC7		0x80
+#define SD_CHECK_CRC16			0x00
+#define SD_NO_CHECK_CRC16		0x40
 #define SD_NO_CHECK_WAIT_CRC_TO		0x20
-#define	SD_WAIT_BUSY_END		0x08
-#define	SD_NO_WAIT_BUSY_END		0x00
-#define	SD_CHECK_CRC7			0x00
-#define	SD_NO_CHECK_CRC7		0x04
-#define	SD_RSP_LEN_0			0x00
-#define	SD_RSP_LEN_6			0x01
-#define	SD_RSP_LEN_17			0x02
+#define SD_WAIT_BUSY_END		0x08
+#define SD_NO_WAIT_BUSY_END		0x00
+#define SD_CHECK_CRC7			0x00
+#define SD_NO_CHECK_CRC7		0x04
+#define SD_RSP_LEN_0			0x00
+#define SD_RSP_LEN_6			0x01
+#define SD_RSP_LEN_17			0x02
 /* SD/MMC Response Type Definition */
-#define	SD_RSP_TYPE_R0			0x04
-#define	SD_RSP_TYPE_R1			0x01
-#define	SD_RSP_TYPE_R1b			0x09
-#define	SD_RSP_TYPE_R2			0x02
-#define	SD_RSP_TYPE_R3			0x05
-#define	SD_RSP_TYPE_R4			0x05
-#define	SD_RSP_TYPE_R5			0x01
-#define	SD_RSP_TYPE_R6			0x01
-#define	SD_RSP_TYPE_R7			0x01
+#define SD_RSP_TYPE_R0			0x04
+#define SD_RSP_TYPE_R1			0x01
+#define SD_RSP_TYPE_R1b			0x09
+#define SD_RSP_TYPE_R2			0x02
+#define SD_RSP_TYPE_R3			0x05
+#define SD_RSP_TYPE_R4			0x05
+#define SD_RSP_TYPE_R5			0x01
+#define SD_RSP_TYPE_R6			0x01
+#define SD_RSP_TYPE_R7			0x01
 
 /* SD_CONFIGURE3 */
-#define	SD_RSP_80CLK_TIMEOUT_EN		0x01
+#define SD_RSP_80CLK_TIMEOUT_EN		0x01
 
 /* Card Transfer Reset Register */
 #define SPI_STOP			0x01
@@ -574,13 +574,13 @@
 
 #define SRCTL				0xFC13
 
-#define	DCM_DRP_CTL			0xFC23
-#define	DCM_DRP_TRIG			0xFC24
-#define	DCM_DRP_CFG			0xFC25
-#define	DCM_DRP_WR_DATA_L		0xFC26
-#define	DCM_DRP_WR_DATA_H		0xFC27
-#define	DCM_DRP_RD_DATA_L		0xFC28
-#define	DCM_DRP_RD_DATA_H		0xFC29
+#define DCM_DRP_CTL			0xFC23
+#define DCM_DRP_TRIG			0xFC24
+#define DCM_DRP_CFG			0xFC25
+#define DCM_DRP_WR_DATA_L		0xFC26
+#define DCM_DRP_WR_DATA_H		0xFC27
+#define DCM_DRP_RD_DATA_L		0xFC28
+#define DCM_DRP_RD_DATA_H		0xFC29
 #define SD_VPCLK0_CTL			0xFC2A
 #define SD_VPCLK1_CTL			0xFC2B
 #define SD_DCMPS0_CTL			0xFC2C
-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [RESEND PATCH v2 2/9] mfd: rtsx: place register address and values togather
  2015-01-22  7:30 [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A micky_ching
  2015-01-22  7:30 ` [RESEND PATCH v2 1/9] mfd: rtsx: replace TAB by SPC after #define micky_ching
@ 2015-01-22  7:30 ` micky_ching
  2015-01-22  7:30 ` [RESEND PATCH v2 3/9] mfd: rtsx: update PETXCFG address micky_ching
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 19+ messages in thread
From: micky_ching @ 2015-01-22  7:30 UTC (permalink / raw)
  To: sameo, lee.jones
  Cc: devel, linux-kernel, gregkh, rogerable, wei_wang, Micky Ching

From: Micky Ching <micky_ching@realsil.com.cn>

It is more readable to place register address and values define
togather. The values define add two leading space indicate belong
to the register address defined above.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
 include/linux/mfd/rtsx_pci.h | 836 +++++++++++++++++++------------------------
 1 file changed, 369 insertions(+), 467 deletions(-)

diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index a9c2a14..e81f2bb 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -28,74 +28,72 @@
 
 #define MAX_RW_REG_CNT			1024
 
-/* PCI Operation Register Address */
 #define RTSX_HCBAR			0x00
 #define RTSX_HCBCTLR			0x04
+#define   STOP_CMD			(0x01 << 28)
+#define   READ_REG_CMD			0
+#define   WRITE_REG_CMD			1
+#define   CHECK_REG_CMD			2
+
 #define RTSX_HDBAR			0x08
+#define   SG_INT			0x04
+#define   SG_END			0x02
+#define   SG_VALID			0x01
+#define   SG_NO_OP			0x00
+#define   SG_TRANS_DATA			(0x02 << 4)
+#define   SG_LINK_DESC			(0x03 << 4)
 #define RTSX_HDBCTLR			0x0C
+#define   SDMA_MODE			0x00
+#define   ADMA_MODE			(0x02 << 26)
+#define   STOP_DMA			(0x01 << 28)
+#define   TRIG_DMA			(0x01 << 31)
+
 #define RTSX_HAIMR			0x10
-#define RTSX_BIPR			0x14
-#define RTSX_BIER			0x18
+#define   HAIMR_TRANS_START		(0x01 << 31)
+#define   HAIMR_READ			0x00
+#define   HAIMR_WRITE			(0x01 << 30)
+#define   HAIMR_READ_START		(HAIMR_TRANS_START | HAIMR_READ)
+#define   HAIMR_WRITE_START		(HAIMR_TRANS_START | HAIMR_WRITE)
+#define   HAIMR_TRANS_END			(HAIMR_TRANS_START)
 
-/* Host command buffer control register */
-#define STOP_CMD			(0x01 << 28)
-
-/* Host data buffer control register */
-#define SDMA_MODE			0x00
-#define ADMA_MODE			(0x02 << 26)
-#define STOP_DMA			(0x01 << 28)
-#define TRIG_DMA			(0x01 << 31)
-
-/* Host access internal memory register */
-#define HAIMR_TRANS_START		(0x01 << 31)
-#define HAIMR_READ			0x00
-#define HAIMR_WRITE			(0x01 << 30)
-#define HAIMR_READ_START		(HAIMR_TRANS_START | HAIMR_READ)
-#define HAIMR_WRITE_START		(HAIMR_TRANS_START | HAIMR_WRITE)
-#define HAIMR_TRANS_END			(HAIMR_TRANS_START)
-
-/* Bus interrupt pending register */
-#define CMD_DONE_INT			(1 << 31)
-#define DATA_DONE_INT			(1 << 30)
-#define TRANS_OK_INT			(1 << 29)
-#define TRANS_FAIL_INT			(1 << 28)
-#define XD_INT				(1 << 27)
-#define MS_INT				(1 << 26)
-#define SD_INT				(1 << 25)
-#define GPIO0_INT			(1 << 24)
-#define OC_INT				(1 << 23)
-#define SD_WRITE_PROTECT		(1 << 19)
-#define XD_EXIST			(1 << 18)
-#define MS_EXIST			(1 << 17)
-#define SD_EXIST			(1 << 16)
-#define DELINK_INT			GPIO0_INT
-#define MS_OC_INT			(1 << 23)
-#define SD_OC_INT			(1 << 22)
+#define RTSX_BIPR			0x14
+#define   CMD_DONE_INT			(1 << 31)
+#define   DATA_DONE_INT			(1 << 30)
+#define   TRANS_OK_INT			(1 << 29)
+#define   TRANS_FAIL_INT		(1 << 28)
+#define   XD_INT			(1 << 27)
+#define   MS_INT			(1 << 26)
+#define   SD_INT			(1 << 25)
+#define   GPIO0_INT			(1 << 24)
+#define   OC_INT			(1 << 23)
+#define   SD_WRITE_PROTECT		(1 << 19)
+#define   XD_EXIST			(1 << 18)
+#define   MS_EXIST			(1 << 17)
+#define   SD_EXIST			(1 << 16)
+#define   DELINK_INT			GPIO0_INT
+#define   MS_OC_INT			(1 << 23)
+#define   SD_OC_INT			(1 << 22)
 
 #define CARD_INT		(XD_INT | MS_INT | SD_INT)
 #define NEED_COMPLETE_INT	(DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
 #define RTSX_INT		(CMD_DONE_INT | NEED_COMPLETE_INT | \
 					CARD_INT | GPIO0_INT | OC_INT)
-
 #define CARD_EXIST		(XD_EXIST | MS_EXIST | SD_EXIST)
 
-/* Bus interrupt enable register */
-#define CMD_DONE_INT_EN		(1 << 31)
-#define DATA_DONE_INT_EN	(1 << 30)
-#define TRANS_OK_INT_EN		(1 << 29)
-#define TRANS_FAIL_INT_EN	(1 << 28)
-#define XD_INT_EN		(1 << 27)
-#define MS_INT_EN		(1 << 26)
-#define SD_INT_EN		(1 << 25)
-#define GPIO0_INT_EN		(1 << 24)
-#define OC_INT_EN		(1 << 23)
-#define DELINK_INT_EN		GPIO0_INT_EN
-#define MS_OC_INT_EN		(1 << 23)
-#define SD_OC_INT_EN		(1 << 22)
-
-#define READ_REG_CMD		0
-#define WRITE_REG_CMD		1
-#define CHECK_REG_CMD		2
+#define RTSX_BIER			0x18
+#define   CMD_DONE_INT_EN		(1 << 31)
+#define   DATA_DONE_INT_EN		(1 << 30)
+#define   TRANS_OK_INT_EN		(1 << 29)
+#define   TRANS_FAIL_INT_EN		(1 << 28)
+#define   XD_INT_EN			(1 << 27)
+#define   MS_INT_EN			(1 << 26)
+#define   SD_INT_EN			(1 << 25)
+#define   GPIO0_INT_EN			(1 << 24)
+#define   OC_INT_EN			(1 << 23)
+#define   DELINK_INT_EN			GPIO0_INT_EN
+#define   MS_OC_INT_EN			(1 << 23)
+#define   SD_OC_INT_EN			(1 << 22)
+
 
 /*
  * macros for easy use
@@ -125,423 +123,68 @@
 #define rtsx_pci_write_config_dword(pcr, where, val) \
 	pci_write_config_dword((pcr)->pci, where, val)
 
-#define STATE_TRANS_NONE	0
-#define STATE_TRANS_CMD		1
-#define STATE_TRANS_BUF		2
-#define STATE_TRANS_SG		3
-
-#define TRANS_NOT_READY		0
-#define TRANS_RESULT_OK		1
-#define TRANS_RESULT_FAIL	2
-#define TRANS_NO_DEVICE		3
-
-#define RTSX_RESV_BUF_LEN	4096
-#define HOST_CMDS_BUF_LEN	1024
-#define HOST_SG_TBL_BUF_LEN	(RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
-#define HOST_SG_TBL_ITEMS	(HOST_SG_TBL_BUF_LEN / 8)
-#define MAX_SG_ITEM_LEN		0x80000
-
-#define HOST_TO_DEVICE		0
-#define DEVICE_TO_HOST		1
-
-#define RTSX_PHASE_MAX		32
-#define RX_TUNING_CNT		3
-
-/* SG descriptor */
-#define SG_INT			0x04
-#define SG_END			0x02
-#define SG_VALID		0x01
-
-#define SG_NO_OP		0x00
-#define SG_TRANS_DATA		(0x02 << 4)
-#define SG_LINK_DESC		(0x03 << 4)
-
-/* Output voltage */
-#define OUTPUT_3V3		0
-#define OUTPUT_1V8		1
-
-/* Card Clock Enable Register */
-#define SD_CLK_EN			0x04
-#define MS_CLK_EN			0x08
-
-/* Card Select Register */
-#define SD_MOD_SEL			2
-#define MS_MOD_SEL			3
-
-/* Card Output Enable Register */
-#define SD_OUTPUT_EN			0x04
-#define MS_OUTPUT_EN			0x08
-
-/* CARD_SHARE_MODE */
-#define CARD_SHARE_MASK			0x0F
-#define CARD_SHARE_MULTI_LUN		0x00
-#define CARD_SHARE_NORMAL		0x00
-#define CARD_SHARE_48_SD		0x04
-#define CARD_SHARE_48_MS		0x08
-/* CARD_SHARE_MODE for barossa */
-#define CARD_SHARE_BAROSSA_SD		0x01
-#define CARD_SHARE_BAROSSA_MS		0x02
-
-/* CARD_DRIVE_SEL */
-#define MS_DRIVE_8mA			(0x01 << 6)
-#define MMC_DRIVE_8mA			(0x01 << 4)
-#define XD_DRIVE_8mA			(0x01 << 2)
-#define GPIO_DRIVE_8mA			0x01
-#define RTS5209_CARD_DRIVE_DEFAULT	(MS_DRIVE_8mA | MMC_DRIVE_8mA |\
-						XD_DRIVE_8mA | GPIO_DRIVE_8mA)
-#define RTL8411_CARD_DRIVE_DEFAULT	(MS_DRIVE_8mA | MMC_DRIVE_8mA |\
-						XD_DRIVE_8mA)
-#define RTSX_CARD_DRIVE_DEFAULT		(MS_DRIVE_8mA | GPIO_DRIVE_8mA)
+#define STATE_TRANS_NONE		0
+#define STATE_TRANS_CMD			1
+#define STATE_TRANS_BUF			2
+#define STATE_TRANS_SG			3
 
-/* SD30_DRIVE_SEL */
-#define DRIVER_TYPE_A			0x05
-#define DRIVER_TYPE_B			0x03
-#define DRIVER_TYPE_C			0x02
-#define DRIVER_TYPE_D			0x01
-#define CFG_DRIVER_TYPE_A		0x02
-#define CFG_DRIVER_TYPE_B		0x03
-#define CFG_DRIVER_TYPE_C		0x01
-#define CFG_DRIVER_TYPE_D		0x00
-
-/* FPDCTL */
-#define SSC_POWER_DOWN			0x01
-#define SD_OC_POWER_DOWN		0x02
-#define ALL_POWER_DOWN			0x07
-#define OC_POWER_DOWN			0x06
-
-/* CLK_CTL */
-#define CHANGE_CLK			0x01
-
-/* LDO_CTL */
-#define BPP_ASIC_1V7			0x00
-#define BPP_ASIC_1V8			0x01
-#define BPP_ASIC_1V9			0x02
-#define BPP_ASIC_2V0			0x03
-#define BPP_ASIC_2V7			0x04
-#define BPP_ASIC_2V8			0x05
-#define BPP_ASIC_3V2			0x06
-#define BPP_ASIC_3V3			0x07
-#define BPP_REG_TUNED18			0x07
-#define BPP_TUNED18_SHIFT_8402		5
-#define BPP_TUNED18_SHIFT_8411		4
-#define BPP_PAD_MASK			0x04
-#define BPP_PAD_3V3			0x04
-#define BPP_PAD_1V8			0x00
-#define BPP_LDO_POWB			0x03
-#define BPP_LDO_ON			0x00
-#define BPP_LDO_SUSPEND			0x02
-#define BPP_LDO_OFF			0x03
-
-/* CD_PAD_CTL */
-#define CD_DISABLE_MASK			0x07
-#define MS_CD_DISABLE			0x04
-#define SD_CD_DISABLE			0x02
-#define XD_CD_DISABLE			0x01
-#define CD_DISABLE			0x07
-#define CD_ENABLE			0x00
-#define MS_CD_EN_ONLY			0x03
-#define SD_CD_EN_ONLY			0x05
-#define XD_CD_EN_ONLY			0x06
-#define FORCE_CD_LOW_MASK		0x38
-#define FORCE_CD_XD_LOW			0x08
-#define FORCE_CD_SD_LOW			0x10
-#define FORCE_CD_MS_LOW			0x20
-#define CD_AUTO_DISABLE			0x40
-
-/* SD_STAT1 */
-#define SD_CRC7_ERR			0x80
-#define SD_CRC16_ERR			0x40
-#define SD_CRC_WRITE_ERR		0x20
-#define SD_CRC_WRITE_ERR_MASK		0x1C
-#define GET_CRC_TIME_OUT		0x02
-#define SD_TUNING_COMPARE_ERR		0x01
-
-/* SD_STAT2 */
-#define SD_RSP_80CLK_TIMEOUT		0x01
-
-/* SD_BUS_STAT */
-#define SD_CLK_TOGGLE_EN		0x80
-#define SD_CLK_FORCE_STOP	        0x40
-#define SD_DAT3_STATUS		        0x10
-#define SD_DAT2_STATUS		        0x08
-#define SD_DAT1_STATUS		        0x04
-#define SD_DAT0_STATUS		        0x02
-#define SD_CMD_STATUS			0x01
-
-/* SD_PAD_CTL */
-#define SD_IO_USING_1V8		        0x80
-#define SD_IO_USING_3V3		        0x7F
-#define TYPE_A_DRIVING		        0x00
-#define TYPE_B_DRIVING			0x01
-#define TYPE_C_DRIVING			0x02
-#define TYPE_D_DRIVING		        0x03
-
-/* SD_SAMPLE_POINT_CTL */
-#define DDR_FIX_RX_DAT			0x00
-#define DDR_VAR_RX_DAT			0x80
-#define DDR_FIX_RX_DAT_EDGE		0x00
-#define DDR_FIX_RX_DAT_14_DELAY		0x40
-#define DDR_FIX_RX_CMD			0x00
-#define DDR_VAR_RX_CMD			0x20
-#define DDR_FIX_RX_CMD_POS_EDGE		0x00
-#define DDR_FIX_RX_CMD_14_DELAY		0x10
-#define SD20_RX_POS_EDGE		0x00
-#define SD20_RX_14_DELAY		0x08
-#define SD20_RX_SEL_MASK		0x08
+#define TRANS_NOT_READY			0
+#define TRANS_RESULT_OK			1
+#define TRANS_RESULT_FAIL		2
+#define TRANS_NO_DEVICE			3
 
-/* SD_PUSH_POINT_CTL */
-#define DDR_FIX_TX_CMD_DAT		0x00
-#define DDR_VAR_TX_CMD_DAT		0x80
-#define DDR_FIX_TX_DAT_14_TSU		0x00
-#define DDR_FIX_TX_DAT_12_TSU		0x40
-#define DDR_FIX_TX_CMD_NEG_EDGE		0x00
-#define DDR_FIX_TX_CMD_14_AHEAD		0x20
-#define SD20_TX_NEG_EDGE		0x00
-#define SD20_TX_14_AHEAD		0x10
-#define SD20_TX_SEL_MASK		0x10
-#define DDR_VAR_SDCLK_POL_SWAP		0x01
-
-/* SD_TRANSFER */
-#define SD_TRANSFER_START		0x80
-#define SD_TRANSFER_END			0x40
-#define SD_STAT_IDLE			0x20
-#define SD_TRANSFER_ERR			0x10
-/* SD Transfer Mode definition */
-#define SD_TM_NORMAL_WRITE		0x00
-#define SD_TM_AUTO_WRITE_3		0x01
-#define SD_TM_AUTO_WRITE_4		0x02
-#define SD_TM_AUTO_READ_3		0x05
-#define SD_TM_AUTO_READ_4		0x06
-#define SD_TM_CMD_RSP			0x08
-#define SD_TM_AUTO_WRITE_1		0x09
-#define SD_TM_AUTO_WRITE_2		0x0A
-#define SD_TM_NORMAL_READ		0x0C
-#define SD_TM_AUTO_READ_1		0x0D
-#define SD_TM_AUTO_READ_2		0x0E
-#define SD_TM_AUTO_TUNING		0x0F
-
-/* SD_VPTX_CTL / SD_VPRX_CTL */
-#define PHASE_CHANGE			0x80
-#define PHASE_NOT_RESET			0x40
-
-/* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
-#define DCMPS_CHANGE			0x80
-#define DCMPS_CHANGE_DONE		0x40
-#define DCMPS_ERROR			0x20
-#define DCMPS_CURRENT_PHASE		0x1F
-
-/* SD Configure 1 Register */
-#define SD_CLK_DIVIDE_0			0x00
-#define SD_CLK_DIVIDE_256		0xC0
-#define SD_CLK_DIVIDE_128		0x80
-#define SD_BUS_WIDTH_1BIT		0x00
-#define SD_BUS_WIDTH_4BIT		0x01
-#define SD_BUS_WIDTH_8BIT		0x02
-#define SD_ASYNC_FIFO_NOT_RST		0x10
-#define SD_20_MODE			0x00
-#define SD_DDR_MODE			0x04
-#define SD_30_MODE			0x08
-
-#define SD_CLK_DIVIDE_MASK		0xC0
-
-/* SD_CMD_STATE */
-#define SD_CMD_IDLE			0x80
-
-/* SD_DATA_STATE */
-#define SD_DATA_IDLE			0x80
-
-/* DCM_DRP_CTL */
-#define DCM_RESET			0x08
-#define DCM_LOCKED			0x04
-#define DCM_208M			0x00
-#define DCM_TX			        0x01
-#define DCM_RX			        0x02
-
-/* DCM_DRP_TRIG */
-#define DRP_START			0x80
-#define DRP_DONE			0x40
-
-/* DCM_DRP_CFG */
-#define DRP_WRITE			0x80
-#define DRP_READ			0x00
-#define DCM_WRITE_ADDRESS_50		0x50
-#define DCM_WRITE_ADDRESS_51		0x51
-#define DCM_READ_ADDRESS_00		0x00
-#define DCM_READ_ADDRESS_51		0x51
-
-/* IRQSTAT0 */
-#define DMA_DONE_INT			0x80
-#define SUSPEND_INT			0x40
-#define LINK_RDY_INT			0x20
-#define LINK_DOWN_INT			0x10
-
-/* DMACTL */
-#define DMA_RST				0x80
-#define DMA_BUSY			0x04
-#define DMA_DIR_TO_CARD			0x00
-#define DMA_DIR_FROM_CARD		0x02
-#define DMA_EN				0x01
-#define DMA_128				(0 << 4)
-#define DMA_256				(1 << 4)
-#define DMA_512				(2 << 4)
-#define DMA_1024			(3 << 4)
-#define DMA_PACK_SIZE_MASK		0x30
-
-/* SSC_CTL1 */
-#define SSC_RSTB			0x80
-#define SSC_8X_EN			0x40
-#define SSC_FIX_FRAC			0x20
-#define SSC_SEL_1M			0x00
-#define SSC_SEL_2M			0x08
-#define SSC_SEL_4M			0x10
-#define SSC_SEL_8M			0x18
-
-/* SSC_CTL2 */
-#define SSC_DEPTH_MASK			0x07
-#define SSC_DEPTH_DISALBE		0x00
-#define SSC_DEPTH_4M			0x01
-#define SSC_DEPTH_2M			0x02
-#define SSC_DEPTH_1M			0x03
-#define SSC_DEPTH_500K			0x04
-#define SSC_DEPTH_250K			0x05
-
-/* System Clock Control Register */
-#define CLK_LOW_FREQ			0x01
-
-/* System Clock Divider Register */
-#define CLK_DIV_1			0x01
-#define CLK_DIV_2			0x02
-#define CLK_DIV_4			0x03
-#define CLK_DIV_8			0x04
-
-/* MS_CFG */
-#define SAMPLE_TIME_RISING		0x00
-#define SAMPLE_TIME_FALLING		0x80
-#define PUSH_TIME_DEFAULT		0x00
-#define PUSH_TIME_ODD			0x40
-#define NO_EXTEND_TOGGLE		0x00
-#define EXTEND_TOGGLE_CHK		0x20
-#define MS_BUS_WIDTH_1			0x00
-#define MS_BUS_WIDTH_4			0x10
-#define MS_BUS_WIDTH_8			0x18
-#define MS_2K_SECTOR_MODE		0x04
-#define MS_512_SECTOR_MODE		0x00
-#define MS_TOGGLE_TIMEOUT_EN		0x00
-#define MS_TOGGLE_TIMEOUT_DISEN		0x01
-#define MS_NO_CHECK_INT			0x02
+#define RTSX_RESV_BUF_LEN		4096
+#define HOST_CMDS_BUF_LEN		1024
+#define HOST_SG_TBL_BUF_LEN		(RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
+#define HOST_SG_TBL_ITEMS		(HOST_SG_TBL_BUF_LEN / 8)
+#define MAX_SG_ITEM_LEN			0x80000
+#define HOST_TO_DEVICE			0
+#define DEVICE_TO_HOST			1
+
+#define OUTPUT_3V3			0
+#define OUTPUT_1V8			1
 
-/* MS_TRANS_CFG */
-#define WAIT_INT			0x80
-#define NO_WAIT_INT			0x00
-#define NO_AUTO_READ_INT_REG		0x00
-#define AUTO_READ_INT_REG		0x40
-#define MS_CRC16_ERR			0x20
-#define MS_RDY_TIMEOUT			0x10
-#define MS_INT_CMDNK			0x08
-#define MS_INT_BREQ			0x04
-#define MS_INT_ERR			0x02
-#define MS_INT_CED			0x01
-
-/* MS_TRANSFER */
-#define MS_TRANSFER_START		0x80
-#define MS_TRANSFER_END			0x40
-#define MS_TRANSFER_ERR			0x20
-#define MS_BS_STATE			0x10
-#define MS_TM_READ_BYTES		0x00
-#define MS_TM_NORMAL_READ		0x01
-#define MS_TM_WRITE_BYTES		0x04
-#define MS_TM_NORMAL_WRITE		0x05
-#define MS_TM_AUTO_READ			0x08
-#define MS_TM_AUTO_WRITE		0x0C
-
-/* SD Configure 2 Register */
-#define SD_CALCULATE_CRC7		0x00
-#define SD_NO_CALCULATE_CRC7		0x80
-#define SD_CHECK_CRC16			0x00
-#define SD_NO_CHECK_CRC16		0x40
-#define SD_NO_CHECK_WAIT_CRC_TO		0x20
-#define SD_WAIT_BUSY_END		0x08
-#define SD_NO_WAIT_BUSY_END		0x00
-#define SD_CHECK_CRC7			0x00
-#define SD_NO_CHECK_CRC7		0x04
-#define SD_RSP_LEN_0			0x00
-#define SD_RSP_LEN_6			0x01
-#define SD_RSP_LEN_17			0x02
-/* SD/MMC Response Type Definition */
-#define SD_RSP_TYPE_R0			0x04
-#define SD_RSP_TYPE_R1			0x01
-#define SD_RSP_TYPE_R1b			0x09
-#define SD_RSP_TYPE_R2			0x02
-#define SD_RSP_TYPE_R3			0x05
-#define SD_RSP_TYPE_R4			0x05
-#define SD_RSP_TYPE_R5			0x01
-#define SD_RSP_TYPE_R6			0x01
-#define SD_RSP_TYPE_R7			0x01
-
-/* SD_CONFIGURE3 */
-#define SD_RSP_80CLK_TIMEOUT_EN		0x01
-
-/* Card Transfer Reset Register */
-#define SPI_STOP			0x01
-#define XD_STOP				0x02
-#define SD_STOP				0x04
-#define MS_STOP				0x08
-#define SPI_CLR_ERR			0x10
-#define XD_CLR_ERR			0x20
-#define SD_CLR_ERR			0x40
-#define MS_CLR_ERR			0x80
-
-/* Card Data Source Register */
-#define PINGPONG_BUFFER			0x01
-#define RING_BUFFER			0x00
-
-/* Card Power Control Register */
-#define PMOS_STRG_MASK			0x10
-#define PMOS_STRG_800mA			0x10
-#define PMOS_STRG_400mA			0x00
-#define SD_POWER_OFF			0x03
-#define SD_PARTIAL_POWER_ON		0x01
-#define SD_POWER_ON			0x00
-#define SD_POWER_MASK			0x03
-#define MS_POWER_OFF			0x0C
-#define MS_PARTIAL_POWER_ON		0x04
-#define MS_POWER_ON			0x00
-#define MS_POWER_MASK			0x0C
-#define BPP_POWER_OFF			0x0F
-#define BPP_POWER_5_PERCENT_ON		0x0E
-#define BPP_POWER_10_PERCENT_ON		0x0C
-#define BPP_POWER_15_PERCENT_ON		0x08
-#define BPP_POWER_ON			0x00
-#define BPP_POWER_MASK			0x0F
-#define SD_VCC_PARTIAL_POWER_ON		0x02
-#define SD_VCC_POWER_ON			0x00
-
-/* PWR_GATE_CTRL */
-#define PWR_GATE_EN			0x01
-#define LDO3318_PWR_MASK		0x06
-#define LDO_ON				0x00
-#define LDO_SUSPEND			0x04
-#define LDO_OFF				0x06
-
-/* CARD_CLK_SOURCE */
-#define CRC_FIX_CLK			(0x00 << 0)
-#define CRC_VAR_CLK0			(0x01 << 0)
-#define CRC_VAR_CLK1			(0x02 << 0)
-#define SD30_FIX_CLK			(0x00 << 2)
-#define SD30_VAR_CLK0			(0x01 << 2)
-#define SD30_VAR_CLK1			(0x02 << 2)
-#define SAMPLE_FIX_CLK			(0x00 << 4)
-#define SAMPLE_VAR_CLK0			(0x01 << 4)
-#define SAMPLE_VAR_CLK1			(0x02 << 4)
-
-/* HOST_SLEEP_STATE */
-#define HOST_ENTER_S1			1
-#define HOST_ENTER_S3			2
+#define RTSX_PHASE_MAX			32
+#define RX_TUNING_CNT			3
 
 #define MS_CFG				0xFD40
+#define   SAMPLE_TIME_RISING		0x00
+#define   SAMPLE_TIME_FALLING		0x80
+#define   PUSH_TIME_DEFAULT		0x00
+#define   PUSH_TIME_ODD			0x40
+#define   NO_EXTEND_TOGGLE		0x00
+#define   EXTEND_TOGGLE_CHK		0x20
+#define   MS_BUS_WIDTH_1		0x00
+#define   MS_BUS_WIDTH_4		0x10
+#define   MS_BUS_WIDTH_8		0x18
+#define   MS_2K_SECTOR_MODE		0x04
+#define   MS_512_SECTOR_MODE		0x00
+#define   MS_TOGGLE_TIMEOUT_EN		0x00
+#define   MS_TOGGLE_TIMEOUT_DISEN	0x01
+#define MS_NO_CHECK_INT			0x02
 #define MS_TPC				0xFD41
 #define MS_TRANS_CFG			0xFD42
+#define   WAIT_INT			0x80
+#define   NO_WAIT_INT			0x00
+#define   NO_AUTO_READ_INT_REG		0x00
+#define   AUTO_READ_INT_REG		0x40
+#define   MS_CRC16_ERR			0x20
+#define   MS_RDY_TIMEOUT		0x10
+#define   MS_INT_CMDNK			0x08
+#define   MS_INT_BREQ			0x04
+#define   MS_INT_ERR			0x02
+#define   MS_INT_CED			0x01
 #define MS_TRANSFER			0xFD43
+#define   MS_TRANSFER_START		0x80
+#define   MS_TRANSFER_END		0x40
+#define   MS_TRANSFER_ERR		0x20
+#define   MS_BS_STATE			0x10
+#define   MS_TM_READ_BYTES		0x00
+#define   MS_TM_NORMAL_READ		0x01
+#define   MS_TM_WRITE_BYTES		0x04
+#define   MS_TM_NORMAL_WRITE		0x05
+#define   MS_TM_AUTO_READ		0x08
+#define   MS_TM_AUTO_WRITE		0x0C
 #define MS_INT_REG			0xFD44
 #define MS_BYTE_CNT			0xFD45
 #define MS_SECTOR_CNT_L			0xFD46
@@ -549,14 +192,90 @@
 #define MS_DBUS_H			0xFD48
 
 #define SD_CFG1				0xFDA0
+#define   SD_CLK_DIVIDE_0		0x00
+#define   SD_CLK_DIVIDE_256		0xC0
+#define   SD_CLK_DIVIDE_128		0x80
+#define   SD_BUS_WIDTH_1BIT		0x00
+#define   SD_BUS_WIDTH_4BIT		0x01
+#define   SD_BUS_WIDTH_8BIT		0x02
+#define   SD_ASYNC_FIFO_NOT_RST		0x10
+#define   SD_20_MODE			0x00
+#define   SD_DDR_MODE			0x04
+#define   SD_30_MODE			0x08
+#define   SD_CLK_DIVIDE_MASK		0xC0
 #define SD_CFG2				0xFDA1
+#define   SD_CALCULATE_CRC7		0x00
+#define   SD_NO_CALCULATE_CRC7		0x80
+#define   SD_CHECK_CRC16		0x00
+#define   SD_NO_CHECK_CRC16		0x40
+#define   SD_NO_CHECK_WAIT_CRC_TO	0x20
+#define   SD_WAIT_BUSY_END		0x08
+#define   SD_NO_WAIT_BUSY_END		0x00
+#define   SD_CHECK_CRC7			0x00
+#define   SD_NO_CHECK_CRC7		0x04
+#define   SD_RSP_LEN_0			0x00
+#define   SD_RSP_LEN_6			0x01
+#define   SD_RSP_LEN_17			0x02
+#define   SD_RSP_TYPE_R0		0x04
+#define   SD_RSP_TYPE_R1		0x01
+#define   SD_RSP_TYPE_R1b		0x09
+#define   SD_RSP_TYPE_R2		0x02
+#define   SD_RSP_TYPE_R3		0x05
+#define   SD_RSP_TYPE_R4		0x05
+#define   SD_RSP_TYPE_R5		0x01
+#define   SD_RSP_TYPE_R6		0x01
+#define   SD_RSP_TYPE_R7		0x01
 #define SD_CFG3				0xFDA2
+#define   SD_RSP_80CLK_TIMEOUT_EN	0x01
+
 #define SD_STAT1			0xFDA3
+#define   SD_CRC7_ERR			0x80
+#define   SD_CRC16_ERR			0x40
+#define   SD_CRC_WRITE_ERR		0x20
+#define   SD_CRC_WRITE_ERR_MASK		0x1C
+#define   GET_CRC_TIME_OUT		0x02
+#define   SD_TUNING_COMPARE_ERR		0x01
 #define SD_STAT2			0xFDA4
+#define   SD_RSP_80CLK_TIMEOUT		0x01
+
 #define SD_BUS_STAT			0xFDA5
+#define   SD_CLK_TOGGLE_EN		0x80
+#define   SD_CLK_FORCE_STOP		0x40
+#define   SD_DAT3_STATUS		0x10
+#define   SD_DAT2_STATUS		0x08
+#define   SD_DAT1_STATUS		0x04
+#define   SD_DAT0_STATUS		0x02
+#define   SD_CMD_STATUS			0x01
 #define SD_PAD_CTL			0xFDA6
+#define   SD_IO_USING_1V8		0x80
+#define   SD_IO_USING_3V3		0x7F
+#define   TYPE_A_DRIVING		0x00
+#define   TYPE_B_DRIVING		0x01
+#define   TYPE_C_DRIVING		0x02
+#define   TYPE_D_DRIVING		0x03
 #define SD_SAMPLE_POINT_CTL		0xFDA7
+#define   DDR_FIX_RX_DAT		0x00
+#define   DDR_VAR_RX_DAT		0x80
+#define   DDR_FIX_RX_DAT_EDGE		0x00
+#define   DDR_FIX_RX_DAT_14_DELAY	0x40
+#define   DDR_FIX_RX_CMD		0x00
+#define   DDR_VAR_RX_CMD		0x20
+#define   DDR_FIX_RX_CMD_POS_EDGE	0x00
+#define   DDR_FIX_RX_CMD_14_DELAY	0x10
+#define   SD20_RX_POS_EDGE		0x00
+#define   SD20_RX_14_DELAY		0x08
+#define SD20_RX_SEL_MASK		0x08
 #define SD_PUSH_POINT_CTL		0xFDA8
+#define   DDR_FIX_TX_CMD_DAT		0x00
+#define   DDR_VAR_TX_CMD_DAT		0x80
+#define   DDR_FIX_TX_DAT_14_TSU		0x00
+#define   DDR_FIX_TX_DAT_12_TSU		0x40
+#define   DDR_FIX_TX_CMD_NEG_EDGE	0x00
+#define   DDR_FIX_TX_CMD_14_AHEAD	0x20
+#define   SD20_TX_NEG_EDGE		0x00
+#define   SD20_TX_14_AHEAD		0x10
+#define   SD20_TX_SEL_MASK		0x10
+#define   DDR_VAR_SDCLK_POL_SWAP	0x01
 #define SD_CMD0				0xFDA9
 #define   SD_CMD_START			0x40
 #define SD_CMD1				0xFDAA
@@ -569,14 +288,46 @@
 #define SD_BLOCK_CNT_L			0xFDB1
 #define SD_BLOCK_CNT_H			0xFDB2
 #define SD_TRANSFER			0xFDB3
+#define   SD_TRANSFER_START		0x80
+#define   SD_TRANSFER_END		0x40
+#define   SD_STAT_IDLE			0x20
+#define   SD_TRANSFER_ERR		0x10
+#define   SD_TM_NORMAL_WRITE		0x00
+#define   SD_TM_AUTO_WRITE_3		0x01
+#define   SD_TM_AUTO_WRITE_4		0x02
+#define   SD_TM_AUTO_READ_3		0x05
+#define   SD_TM_AUTO_READ_4		0x06
+#define   SD_TM_CMD_RSP			0x08
+#define   SD_TM_AUTO_WRITE_1		0x09
+#define   SD_TM_AUTO_WRITE_2		0x0A
+#define   SD_TM_NORMAL_READ		0x0C
+#define   SD_TM_AUTO_READ_1		0x0D
+#define   SD_TM_AUTO_READ_2		0x0E
+#define   SD_TM_AUTO_TUNING		0x0F
 #define SD_CMD_STATE			0xFDB5
+#define   SD_CMD_IDLE			0x80
+
 #define SD_DATA_STATE			0xFDB6
+#define   SD_DATA_IDLE			0x80
 
 #define SRCTL				0xFC13
 
 #define DCM_DRP_CTL			0xFC23
+#define   DCM_RESET			0x08
+#define   DCM_LOCKED			0x04
+#define   DCM_208M			0x00
+#define   DCM_TX			0x01
+#define   DCM_RX			0x02
 #define DCM_DRP_TRIG			0xFC24
+#define   DRP_START			0x80
+#define   DRP_DONE			0x40
 #define DCM_DRP_CFG			0xFC25
+#define   DRP_WRITE			0x80
+#define   DRP_READ			0x00
+#define   DCM_WRITE_ADDRESS_50		0x50
+#define   DCM_WRITE_ADDRESS_51		0x51
+#define   DCM_READ_ADDRESS_00		0x00
+#define   DCM_READ_ADDRESS_51		0x51
 #define DCM_DRP_WR_DATA_L		0xFC26
 #define DCM_DRP_WR_DATA_H		0xFC27
 #define DCM_DRP_RD_DATA_L		0xFC28
@@ -587,42 +338,153 @@
 #define SD_DCMPS1_CTL			0xFC2D
 #define SD_VPTX_CTL			SD_VPCLK0_CTL
 #define SD_VPRX_CTL			SD_VPCLK1_CTL
+#define   PHASE_CHANGE			0x80
+#define   PHASE_NOT_RESET		0x40
 #define SD_DCMPS_TX_CTL			SD_DCMPS0_CTL
 #define SD_DCMPS_RX_CTL			SD_DCMPS1_CTL
+#define   DCMPS_CHANGE			0x80
+#define   DCMPS_CHANGE_DONE		0x40
+#define   DCMPS_ERROR			0x20
+#define   DCMPS_CURRENT_PHASE		0x1F
 #define CARD_CLK_SOURCE			0xFC2E
-
+#define   CRC_FIX_CLK			(0x00 << 0)
+#define   CRC_VAR_CLK0			(0x01 << 0)
+#define   CRC_VAR_CLK1			(0x02 << 0)
+#define   SD30_FIX_CLK			(0x00 << 2)
+#define   SD30_VAR_CLK0			(0x01 << 2)
+#define   SD30_VAR_CLK1			(0x02 << 2)
+#define   SAMPLE_FIX_CLK		(0x00 << 4)
+#define   SAMPLE_VAR_CLK0		(0x01 << 4)
+#define   SAMPLE_VAR_CLK1		(0x02 << 4)
 #define CARD_PWR_CTL			0xFD50
+#define   PMOS_STRG_MASK		0x10
+#define   PMOS_STRG_800mA		0x10
+#define   PMOS_STRG_400mA		0x00
+#define   SD_POWER_OFF			0x03
+#define   SD_PARTIAL_POWER_ON		0x01
+#define   SD_POWER_ON			0x00
+#define   SD_POWER_MASK			0x03
+#define   MS_POWER_OFF			0x0C
+#define   MS_PARTIAL_POWER_ON		0x04
+#define   MS_POWER_ON			0x00
+#define   MS_POWER_MASK			0x0C
+#define   BPP_POWER_OFF			0x0F
+#define   BPP_POWER_5_PERCENT_ON	0x0E
+#define   BPP_POWER_10_PERCENT_ON	0x0C
+#define   BPP_POWER_15_PERCENT_ON	0x08
+#define   BPP_POWER_ON			0x00
+#define   BPP_POWER_MASK		0x0F
+#define   SD_VCC_PARTIAL_POWER_ON	0x02
+#define   SD_VCC_POWER_ON		0x00
 #define CARD_CLK_SWITCH			0xFD51
 #define RTL8411B_PACKAGE_MODE		0xFD51
 #define CARD_SHARE_MODE			0xFD52
+#define   CARD_SHARE_MASK		0x0F
+#define   CARD_SHARE_MULTI_LUN		0x00
+#define   CARD_SHARE_NORMAL		0x00
+#define   CARD_SHARE_48_SD		0x04
+#define   CARD_SHARE_48_MS		0x08
+#define   CARD_SHARE_BAROSSA_SD		0x01
+#define   CARD_SHARE_BAROSSA_MS		0x02
 #define CARD_DRIVE_SEL			0xFD53
+#define   MS_DRIVE_8mA			(0x01 << 6)
+#define   MMC_DRIVE_8mA			(0x01 << 4)
+#define   XD_DRIVE_8mA			(0x01 << 2)
+#define   GPIO_DRIVE_8mA		0x01
+#define RTS5209_CARD_DRIVE_DEFAULT	(MS_DRIVE_8mA | MMC_DRIVE_8mA |\
+					XD_DRIVE_8mA | GPIO_DRIVE_8mA)
+#define RTL8411_CARD_DRIVE_DEFAULT	(MS_DRIVE_8mA | MMC_DRIVE_8mA |\
+					XD_DRIVE_8mA)
+#define RTSX_CARD_DRIVE_DEFAULT		(MS_DRIVE_8mA | GPIO_DRIVE_8mA)
+
 #define CARD_STOP			0xFD54
+#define   SPI_STOP			0x01
+#define   XD_STOP			0x02
+#define   SD_STOP			0x04
+#define   MS_STOP			0x08
+#define   SPI_CLR_ERR			0x10
+#define   XD_CLR_ERR			0x20
+#define   SD_CLR_ERR			0x40
+#define   MS_CLR_ERR			0x80
 #define CARD_OE				0xFD55
+#define   SD_OUTPUT_EN			0x04
+#define   MS_OUTPUT_EN			0x08
 #define CARD_AUTO_BLINK			0xFD56
 #define CARD_GPIO_DIR			0xFD57
 #define CARD_GPIO			0xFD58
 #define CARD_DATA_SOURCE		0xFD5B
+#define   PINGPONG_BUFFER		0x01
+#define   RING_BUFFER			0x00
 #define SD30_CLK_DRIVE_SEL		0xFD5A
+#define   DRIVER_TYPE_A			0x05
+#define   DRIVER_TYPE_B			0x03
+#define   DRIVER_TYPE_C			0x02
+#define   DRIVER_TYPE_D			0x01
 #define CARD_SELECT			0xFD5C
+#define   SD_MOD_SEL			2
+#define   MS_MOD_SEL			3
 #define SD30_DRIVE_SEL			0xFD5E
+#define   CFG_DRIVER_TYPE_A		0x02
+#define   CFG_DRIVER_TYPE_B		0x03
+#define   CFG_DRIVER_TYPE_C		0x01
+#define   CFG_DRIVER_TYPE_D		0x00
 #define SD30_CMD_DRIVE_SEL		0xFD5E
 #define SD30_DAT_DRIVE_SEL		0xFD5F
 #define CARD_CLK_EN			0xFD69
+#define   SD_CLK_EN			0x04
+#define   MS_CLK_EN			0x08
 #define SDIO_CTRL			0xFD6B
 #define CD_PAD_CTL			0xFD73
-
+#define   CD_DISABLE_MASK		0x07
+#define   MS_CD_DISABLE			0x04
+#define   SD_CD_DISABLE			0x02
+#define   XD_CD_DISABLE			0x01
+#define   CD_DISABLE			0x07
+#define   CD_ENABLE			0x00
+#define   MS_CD_EN_ONLY			0x03
+#define   SD_CD_EN_ONLY			0x05
+#define   XD_CD_EN_ONLY			0x06
+#define   FORCE_CD_LOW_MASK		0x38
+#define   FORCE_CD_XD_LOW		0x08
+#define   FORCE_CD_SD_LOW		0x10
+#define   FORCE_CD_MS_LOW		0x20
+#define   CD_AUTO_DISABLE		0x40
 #define FPDCTL				0xFC00
+#define   SSC_POWER_DOWN		0x01
+#define   SD_OC_POWER_DOWN		0x02
+#define   ALL_POWER_DOWN		0x07
+#define   OC_POWER_DOWN			0x06
 #define PDINFO				0xFC01
 
 #define CLK_CTL				0xFC02
+#define   CHANGE_CLK			0x01
+#define   CLK_LOW_FREQ			0x01
+
 #define CLK_DIV				0xFC03
+#define   CLK_DIV_1			0x01
+#define   CLK_DIV_2			0x02
+#define   CLK_DIV_4			0x03
+#define   CLK_DIV_8			0x04
 #define CLK_SEL				0xFC04
 
 #define SSC_DIV_N_0			0xFC0F
 #define SSC_DIV_N_1			0xFC10
 #define SSC_CTL1			0xFC11
+#define    SSC_RSTB			0x80
+#define    SSC_8X_EN			0x40
+#define    SSC_FIX_FRAC			0x20
+#define    SSC_SEL_1M			0x00
+#define    SSC_SEL_2M			0x08
+#define    SSC_SEL_4M			0x10
+#define    SSC_SEL_8M			0x18
 #define SSC_CTL2			0xFC12
-
+#define    SSC_DEPTH_MASK		0x07
+#define    SSC_DEPTH_DISALBE		0x00
+#define    SSC_DEPTH_4M			0x01
+#define    SSC_DEPTH_2M			0x02
+#define    SSC_DEPTH_1M			0x03
+#define    SSC_DEPTH_500K		0x04
+#define    SSC_DEPTH_250K		0x05
 #define RCCTL				0xFC14
 
 #define FPGA_PULL_CTL			0xFC1D
@@ -630,6 +492,24 @@
 #define GPIO_CTL			0xFC1F
 
 #define LDO_CTL				0xFC1E
+#define   BPP_ASIC_1V7			0x00
+#define   BPP_ASIC_1V8			0x01
+#define   BPP_ASIC_1V9			0x02
+#define   BPP_ASIC_2V0			0x03
+#define   BPP_ASIC_2V7			0x04
+#define   BPP_ASIC_2V8			0x05
+#define   BPP_ASIC_3V2			0x06
+#define   BPP_ASIC_3V3			0x07
+#define   BPP_REG_TUNED18		0x07
+#define   BPP_TUNED18_SHIFT_8402	5
+#define   BPP_TUNED18_SHIFT_8411	4
+#define   BPP_PAD_MASK			0x04
+#define   BPP_PAD_3V3			0x04
+#define   BPP_PAD_1V8			0x00
+#define   BPP_LDO_POWB			0x03
+#define   BPP_LDO_ON			0x00
+#define   BPP_LDO_SUSPEND		0x02
+#define   BPP_LDO_OFF			0x03
 #define SYS_VER				0xFC32
 
 #define CARD_PULL_CTL1			0xFD60
@@ -642,6 +522,10 @@
 /* PCI Express Related Registers */
 #define IRQEN0				0xFE20
 #define IRQSTAT0			0xFE21
+#define    DMA_DONE_INT			0x80
+#define    SUSPEND_INT			0x40
+#define    LINK_RDY_INT			0x20
+#define    LINK_DOWN_INT		0x10
 #define IRQEN1				0xFE22
 #define IRQSTAT1			0xFE23
 #define TLPRIEN				0xFE24
@@ -653,6 +537,16 @@
 #define DMATC2				0xFE2A
 #define DMATC3				0xFE2B
 #define DMACTL				0xFE2C
+#define   DMA_RST			0x80
+#define   DMA_BUSY			0x04
+#define   DMA_DIR_TO_CARD		0x00
+#define   DMA_DIR_FROM_CARD		0x02
+#define   DMA_EN			0x01
+#define   DMA_128			(0 << 4)
+#define   DMA_256			(1 << 4)
+#define   DMA_512			(2 << 4)
+#define   DMA_1024			(3 << 4)
+#define   DMA_PACK_SIZE_MASK		0x30
 #define BCTL				0xFE2D
 #define RBBC0				0xFE2E
 #define RBBC1				0xFE2F
@@ -693,11 +587,19 @@
 #define RESET_LOAD_REG			0xFE5E
 #define EFUSE_CONTENT			0xFE5F
 #define HOST_SLEEP_STATE		0xFE60
+#define   HOST_ENTER_S1			1
+#define   HOST_ENTER_S3			2
+
 #define SDIO_CFG			0xFE70
 
 #define NFTS_TX_CTRL			0xFE72
 
 #define PWR_GATE_CTRL			0xFE75
+#define   PWR_GATE_EN			0x01
+#define   LDO3318_PWR_MASK		0x06
+#define   LDO_ON			0x00
+#define   LDO_SUSPEND			0x04
+#define   LDO_OFF			0x06
 #define PWD_SUSPEND_EN			0xFE76
 #define LDO_PWR_SEL			0xFE78
 
-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [RESEND PATCH v2 3/9] mfd: rtsx: update PETXCFG address
  2015-01-22  7:30 [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A micky_ching
  2015-01-22  7:30 ` [RESEND PATCH v2 1/9] mfd: rtsx: replace TAB by SPC after #define micky_ching
  2015-01-22  7:30 ` [RESEND PATCH v2 2/9] mfd: rtsx: place register address and values togather micky_ching
@ 2015-01-22  7:30 ` micky_ching
  2015-01-22  7:30 ` [RESEND PATCH v2 4/9] mfd: rtsx: update driving settings micky_ching
                   ` (5 subsequent siblings)
  8 siblings, 0 replies; 19+ messages in thread
From: micky_ching @ 2015-01-22  7:30 UTC (permalink / raw)
  To: sameo, lee.jones
  Cc: devel, linux-kernel, gregkh, rogerable, wei_wang, Micky Ching

From: Micky Ching <micky_ching@realsil.com.cn>

PETXCFG is defined at 0xFF03, the old 0xFE49 not used any more.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/mfd/rts5227.c        | 6 ++----
 drivers/mfd/rts5249.c        | 6 ++----
 include/linux/mfd/rtsx_pci.h | 2 +-
 3 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/mfd/rts5227.c b/drivers/mfd/rts5227.c
index 3240740..1f387d4 100644
--- a/drivers/mfd/rts5227.c
+++ b/drivers/mfd/rts5227.c
@@ -118,11 +118,9 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
 	rts5227_fill_driving(pcr, OUTPUT_3V3);
 	/* Configure force_clock_req */
 	if (pcr->flags & PCR_REVERSE_SOCKET)
-		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
-				AUTOLOAD_CFG_BASE + 3, 0xB8, 0xB8);
+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
 	else
-		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
-				AUTOLOAD_CFG_BASE + 3, 0xB8, 0x88);
+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
 
 	return rtsx_pci_send_cmd(pcr, 100);
diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
index cf425cc..225ad55 100644
--- a/drivers/mfd/rts5249.c
+++ b/drivers/mfd/rts5249.c
@@ -116,11 +116,9 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
 	/* Configure driving */
 	rts5249_fill_driving(pcr, OUTPUT_3V3);
 	if (pcr->flags & PCR_REVERSE_SOCKET)
-		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
-				AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
 	else
-		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
-				AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
+		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
 
 	return rtsx_pci_send_cmd(pcr, 100);
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index e81f2bb..87cff60 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -572,7 +572,6 @@
 #define MSGTXDATA2			0xFE46
 #define MSGTXDATA3			0xFE47
 #define MSGTXCTL			0xFE48
-#define PETXCFG				0xFE49
 #define LTR_CTL				0xFE4A
 #define OBFF_CFG			0xFE4C
 
@@ -606,6 +605,7 @@
 #define DUMMY_REG_RESET_0		0xFE90
 
 #define AUTOLOAD_CFG_BASE		0xFF00
+#define PETXCFG				0xFF03
 
 #define PM_CTRL1			0xFF44
 #define PM_CTRL2			0xFF45
-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [RESEND PATCH v2 4/9] mfd: rtsx: update driving settings
  2015-01-22  7:30 [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A micky_ching
                   ` (2 preceding siblings ...)
  2015-01-22  7:30 ` [RESEND PATCH v2 3/9] mfd: rtsx: update PETXCFG address micky_ching
@ 2015-01-22  7:30 ` micky_ching
  2015-01-22  7:40   ` Joe Perches
  2015-01-22  7:30 ` [RESEND PATCH v2 5/9] mfd: rtsx: update phy register micky_ching
                   ` (4 subsequent siblings)
  8 siblings, 1 reply; 19+ messages in thread
From: micky_ching @ 2015-01-22  7:30 UTC (permalink / raw)
  To: sameo, lee.jones
  Cc: devel, linux-kernel, gregkh, rogerable, wei_wang, Micky Ching

From: Micky Ching <micky_ching@realsil.com.cn>

update card drive settings, This setting can be used for rts5249
rts524A and rts525A.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/mfd/rts5249.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
index 225ad55..2fe2854 100644
--- a/drivers/mfd/rts5249.c
+++ b/drivers/mfd/rts5249.c
@@ -36,16 +36,16 @@ static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
 {
 	u8 driving_3v3[4][3] = {
-		{0x11, 0x11, 0x11},
+		{0x11, 0x11, 0x18},
 		{0x55, 0x55, 0x5C},
-		{0x99, 0x99, 0x92},
-		{0x99, 0x99, 0x92},
+		{0xFF, 0xFF, 0xFF},
+		{0x96, 0x96, 0x96},
 	};
 	u8 driving_1v8[4][3] = {
+		{0xC4, 0xC4, 0xC4},
 		{0x3C, 0x3C, 0x3C},
-		{0xB3, 0xB3, 0xB3},
 		{0xFE, 0xFE, 0xFE},
-		{0xC4, 0xC4, 0xC4},
+		{0xB3, 0xB3, 0xB3},
 	};
 	u8 (*driving)[3], drive_sel;
 
@@ -341,7 +341,7 @@ void rts5249_init_params(struct rtsx_pcr *pcr)
 
 	pcr->flags = 0;
 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
-	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
+	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 	pcr->aspm_en = ASPM_L1_EN;
 	pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16);
-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [RESEND PATCH v2 5/9] mfd: rtsx: update phy register
  2015-01-22  7:30 [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A micky_ching
                   ` (3 preceding siblings ...)
  2015-01-22  7:30 ` [RESEND PATCH v2 4/9] mfd: rtsx: update driving settings micky_ching
@ 2015-01-22  7:30 ` micky_ching
  2015-02-16 14:07   ` Lee Jones
  2015-01-22  7:30 ` [RESEND PATCH v2 6/9] mfd: rtsx: remove LCTLR defination micky_ching
                   ` (3 subsequent siblings)
  8 siblings, 1 reply; 19+ messages in thread
From: micky_ching @ 2015-01-22  7:30 UTC (permalink / raw)
  To: sameo, lee.jones
  Cc: devel, linux-kernel, gregkh, rogerable, wei_wang, Micky Ching

From: Micky Ching <micky_ching@realsil.com.cn>

update phy register value and using direct value instead of macros.
It is much easier to debug using constant value than a lot of macros.
We usually need compare the value directly to check the configure.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
---
 drivers/mfd/rts5249.c        |  55 ++++++++++++----------
 include/linux/mfd/rtsx_pci.h | 109 ++++++++++++++++++++++---------------------
 2 files changed, 85 insertions(+), 79 deletions(-)

diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
index 2fe2854..d8072f6 100644
--- a/drivers/mfd/rts5249.c
+++ b/drivers/mfd/rts5249.c
@@ -132,57 +132,62 @@ static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
 	if (err < 0)
 		return err;
 
-	err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV,
-			PHY_REG_REV_RESV | PHY_REG_REV_RXIDLE_LATCHED |
-			PHY_REG_REV_P1_EN | PHY_REG_REV_RXIDLE_EN |
-			PHY_REG_REV_RX_PWST | PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 |
-			PHY_REG_REV_STOP_CLKRD | PHY_REG_REV_STOP_CLKWR);
+	err = rtsx_pci_write_phy_register(pcr, PHY_REV,
+		PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
+		PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
+		PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
+		PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
+		PHY_REV_STOP_CLKWR);
 	if (err < 0)
 		return err;
 
 	msleep(1);
 
 	err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
-			PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
-			PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
+		PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
+		PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
 	if (err < 0)
 		return err;
+
 	err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
-			PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
-			PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
-			PHY_PCR_RSSI_EN);
+		PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
+		PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
+		PHY_PCR_RSSI_EN | PHY_PCR_RX10K);
 	if (err < 0)
 		return err;
+
 	err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
-			PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
-			PHY_RCR2_CDR_CP_10 | PHY_RCR2_CDR_SR_2 |
-			PHY_RCR2_FREQSEL_12 | PHY_RCR2_CPADJEN |
-			PHY_RCR2_CDR_SC_8 | PHY_RCR2_CALIB_LATE);
+		PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR |
+		PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 |
+		PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE);
 	if (err < 0)
 		return err;
+
 	err = rtsx_pci_write_phy_register(pcr, PHY_FLD4,
-			PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
-			PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
-			PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
-			PHY_FLD4_BER_CHK_EN);
+		PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF |
+		PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA |
+		PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER |
+		PHY_FLD4_BER_CHK_EN);
 	if (err < 0)
 		return err;
-	err = rtsx_pci_write_phy_register(pcr, PHY_RDR, PHY_RDR_RXDSEL_1_9);
+	err = rtsx_pci_write_phy_register(pcr, PHY_RDR,
+		PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD);
 	if (err < 0)
 		return err;
 	err = rtsx_pci_write_phy_register(pcr, PHY_RCR1,
-			PHY_RCR1_ADP_TIME | PHY_RCR1_VCO_COARSE);
+		PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE);
 	if (err < 0)
 		return err;
 	err = rtsx_pci_write_phy_register(pcr, PHY_FLD3,
-			PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
-			PHY_FLD3_RXDELINK);
+		PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 |
+		PHY_FLD3_RXDELINK);
 	if (err < 0)
 		return err;
+
 	return rtsx_pci_write_phy_register(pcr, PHY_TUNE,
-			PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
-			PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
-			PHY_TUNE_TUNED12);
+		PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 |
+		PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 |
+		PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
 }
 
 static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 87cff60..0103210 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -630,16 +630,47 @@
 
 /* Phy register */
 #define PHY_PCR				0x00
+#define   PHY_PCR_FORCE_CODE		0xB000
+#define   PHY_PCR_OOBS_CALI_50		0x0800
+#define   PHY_PCR_OOBS_VCM_08		0x0200
+#define   PHY_PCR_OOBS_SEN_90		0x0040
+#define   PHY_PCR_RSSI_EN		0x0002
+#define   PHY_PCR_RX10K			0x0001
+
 #define PHY_RCR0			0x01
 #define PHY_RCR1			0x02
+#define   PHY_RCR1_ADP_TIME_4		0x0400
+#define   PHY_RCR1_VCO_COARSE		0x001F
+
 #define PHY_RCR2			0x03
+#define   PHY_RCR2_EMPHASE_EN		0x8000
+#define   PHY_RCR2_NADJR		0x4000
+#define   PHY_RCR2_CDR_SR_2		0x0100
+#define   PHY_RCR2_FREQSEL_12		0x0040
+#define   PHY_RCR2_CDR_SC_12P		0x0010
+#define   PHY_RCR2_CALIB_LATE		0x0002
+
 #define PHY_RTCR			0x04
 #define PHY_RDR				0x05
+#define   PHY_RDR_RXDSEL_1_9		0x4000
+#define   PHY_SSC_AUTO_PWD		0x0600
 #define PHY_TCR0			0x06
 #define PHY_TCR1			0x07
 #define PHY_TUNE			0x08
+#define   PHY_TUNE_TUNEREF_1_0		0x4000
+#define   PHY_TUNE_VBGSEL_1252		0x0C00
+#define   PHY_TUNE_SDBUS_33		0x0200
+#define   PHY_TUNE_TUNED18		0x01C0
+#define   PHY_TUNE_TUNED12		0X0020
+#define   PHY_TUNE_TUNEA12		0x0004
+
 #define PHY_IMR				0x09
 #define PHY_BPCR			0x0A
+#define   PHY_BPCR_IBRXSEL		0x0400
+#define   PHY_BPCR_IBTXSEL		0x0100
+#define   PHY_BPCR_IB_FILTER		0x0080
+#define   PHY_BPCR_CMIRROR_EN		0x0040
+
 #define PHY_BIST			0x0B
 #define PHY_RAW_L			0x0C
 #define PHY_RAW_H			0x0D
@@ -654,12 +685,35 @@
 #define PHY_BPNR			0x16
 #define PHY_BRNR2			0x17
 #define PHY_BENR			0x18
-#define PHY_REG_REV			0x19
+#define PHY_REV				0x19
+#define   PHY_REV_RESV			0xE000
+#define   PHY_REV_RXIDLE_LATCHED	0x1000
+#define   PHY_REV_P1_EN			0x0800
+#define   PHY_REV_RXIDLE_EN		0x0400
+#define   PHY_REV_CLKREQ_TX_EN		0x0200
+#define   PHY_REV_CLKREQ_RX_EN		0x0100
+#define   PHY_REV_CLKREQ_DT_1_0		0x0040
+#define   PHY_REV_STOP_CLKRD		0x0020
+#define   PHY_REV_RX_PWST		0x0008
+#define   PHY_REV_STOP_CLKWR		0x0004
+
 #define PHY_FLD0			0x1A
 #define PHY_FLD1			0x1B
 #define PHY_FLD2			0x1C
 #define PHY_FLD3			0x1D
+#define   PHY_FLD3_TIMER_4		0x0800
+#define   PHY_FLD3_TIMER_6		0x0020
+#define   PHY_FLD3_RXDELINK		0x0004
+
 #define PHY_FLD4			0x1E
+#define   PHY_FLD4_FLDEN_SEL		0x4000
+#define   PHY_FLD4_REQ_REF		0x2000
+#define   PHY_FLD4_RXAMP_OFF		0x1000
+#define   PHY_FLD4_REQ_ADDA		0x0800
+#define   PHY_FLD4_BER_COUNT		0x00E0
+#define   PHY_FLD4_BER_TIMER		0x000A
+#define   PHY_FLD4_BER_CHK_EN		0x0001
+
 #define PHY_DUM_REG			0x1F
 
 #define LCTLR				0x80
@@ -675,59 +729,6 @@
 #define PCR_SETTING_REG2		0x814
 #define PCR_SETTING_REG3		0x747
 
-/* Phy bits */
-#define PHY_PCR_FORCE_CODE			0xB000
-#define PHY_PCR_OOBS_CALI_50			0x0800
-#define PHY_PCR_OOBS_VCM_08			0x0200
-#define PHY_PCR_OOBS_SEN_90			0x0040
-#define PHY_PCR_RSSI_EN				0x0002
-
-#define PHY_RCR1_ADP_TIME			0x0100
-#define PHY_RCR1_VCO_COARSE			0x001F
-
-#define PHY_RCR2_EMPHASE_EN			0x8000
-#define PHY_RCR2_NADJR				0x4000
-#define PHY_RCR2_CDR_CP_10			0x0400
-#define PHY_RCR2_CDR_SR_2			0x0100
-#define PHY_RCR2_FREQSEL_12			0x0040
-#define PHY_RCR2_CPADJEN			0x0020
-#define PHY_RCR2_CDR_SC_8			0x0008
-#define PHY_RCR2_CALIB_LATE			0x0002
-
-#define PHY_RDR_RXDSEL_1_9			0x4000
-
-#define PHY_TUNE_TUNEREF_1_0			0x4000
-#define PHY_TUNE_VBGSEL_1252			0x0C00
-#define PHY_TUNE_SDBUS_33			0x0200
-#define PHY_TUNE_TUNED18			0x01C0
-#define PHY_TUNE_TUNED12			0X0020
-
-#define PHY_BPCR_IBRXSEL			0x0400
-#define PHY_BPCR_IBTXSEL			0x0100
-#define PHY_BPCR_IB_FILTER			0x0080
-#define PHY_BPCR_CMIRROR_EN			0x0040
-
-#define PHY_REG_REV_RESV			0xE000
-#define PHY_REG_REV_RXIDLE_LATCHED		0x1000
-#define PHY_REG_REV_P1_EN			0x0800
-#define PHY_REG_REV_RXIDLE_EN			0x0400
-#define PHY_REG_REV_CLKREQ_DLY_TIMER_1_0	0x0040
-#define PHY_REG_REV_STOP_CLKRD			0x0020
-#define PHY_REG_REV_RX_PWST			0x0008
-#define PHY_REG_REV_STOP_CLKWR			0x0004
-
-#define PHY_FLD3_TIMER_4			0x7800
-#define PHY_FLD3_TIMER_6			0x00E0
-#define PHY_FLD3_RXDELINK			0x0004
-
-#define PHY_FLD4_FLDEN_SEL			0x4000
-#define PHY_FLD4_REQ_REF			0x2000
-#define PHY_FLD4_RXAMP_OFF			0x1000
-#define PHY_FLD4_REQ_ADDA			0x0800
-#define PHY_FLD4_BER_COUNT			0x00E0
-#define PHY_FLD4_BER_TIMER			0x000A
-#define PHY_FLD4_BER_CHK_EN			0x0001
-
 #define rtsx_pci_init_cmd(pcr)		((pcr)->ci = 0)
 
 struct rtsx_pcr;
-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [RESEND PATCH v2 6/9] mfd: rtsx: remove LCTLR defination
  2015-01-22  7:30 [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A micky_ching
                   ` (4 preceding siblings ...)
  2015-01-22  7:30 ` [RESEND PATCH v2 5/9] mfd: rtsx: update phy register micky_ching
@ 2015-01-22  7:30 ` micky_ching
  2015-02-16 14:31   ` Lee Jones
  2015-01-22  7:30 ` [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A micky_ching
                   ` (2 subsequent siblings)
  8 siblings, 1 reply; 19+ messages in thread
From: micky_ching @ 2015-01-22  7:30 UTC (permalink / raw)
  To: sameo, lee.jones
  Cc: devel, linux-kernel, gregkh, rogerable, wei_wang, Micky Ching

From: Micky Ching <micky_ching@realsil.com.cn>

To enable/disable ASPM we should find LINK CONTROL register
in PCI config space. All old chip use 0x80 address, but new
chip may use another address, so we using pci_find_capability()
to get LINK CONTROL address.

rtsx_gops.c was removed, we consider to put some common operations
to this file, but the actual thing is, only a group of chips
are in common ops1, and another group of chips in common ops2,
it is hard to decide put which ops into generic ops file.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
---
 drivers/mfd/Makefile         |  2 +-
 drivers/mfd/rts5227.c        |  2 +-
 drivers/mfd/rts5249.c        |  3 +--
 drivers/mfd/rtsx_gops.c      | 37 -------------------------------------
 drivers/mfd/rtsx_pcr.c       | 22 +++++++++++++++++-----
 include/linux/mfd/rtsx_pci.h | 10 +---------
 6 files changed, 21 insertions(+), 55 deletions(-)
 delete mode 100644 drivers/mfd/rtsx_gops.c

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 53467e2..2cd7e74 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_MFD_CROS_EC)	+= cros_ec.o
 obj-$(CONFIG_MFD_CROS_EC_I2C)	+= cros_ec_i2c.o
 obj-$(CONFIG_MFD_CROS_EC_SPI)	+= cros_ec_spi.o
 
-rtsx_pci-objs			:= rtsx_pcr.o rtsx_gops.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o
+rtsx_pci-objs			:= rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o
 obj-$(CONFIG_MFD_RTSX_PCI)	+= rtsx_pci.o
 obj-$(CONFIG_MFD_RTSX_USB)	+= rtsx_usb.o
 
diff --git a/drivers/mfd/rts5227.c b/drivers/mfd/rts5227.c
index 1f387d4..0c02831 100644
--- a/drivers/mfd/rts5227.c
+++ b/drivers/mfd/rts5227.c
@@ -130,7 +130,7 @@ static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
 {
 	int err;
 
-	err = rtsx_gops_pm_reset(pcr);
+	err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
 	if (err < 0)
 		return err;
 
diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
index d8072f6..3977946 100644
--- a/drivers/mfd/rts5249.c
+++ b/drivers/mfd/rts5249.c
@@ -119,7 +119,6 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
 	else
 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
-	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
 
 	return rtsx_pci_send_cmd(pcr, 100);
 }
@@ -128,7 +127,7 @@ static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
 {
 	int err;
 
-	err = rtsx_gops_pm_reset(pcr);
+	err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
 	if (err < 0)
 		return err;
 
diff --git a/drivers/mfd/rtsx_gops.c b/drivers/mfd/rtsx_gops.c
deleted file mode 100644
index b1a98c6..0000000
--- a/drivers/mfd/rtsx_gops.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Driver for Realtek PCI-Express card reader
- *
- * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2, or (at your option) any
- * later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- * Author:
- *   Micky Ching <micky_ching@realsil.com.cn>
- */
-
-#include <linux/mfd/rtsx_pci.h>
-#include "rtsx_pcr.h"
-
-int rtsx_gops_pm_reset(struct rtsx_pcr *pcr)
-{
-	int err;
-
-	/* init aspm */
-	rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0x00);
-	err = rtsx_pci_update_cfg_byte(pcr, LCTLR, ~LCTLR_ASPM_CTL_MASK, 0x00);
-	if (err < 0)
-		return err;
-
-	/* reset PM_CTRL3 before send buffer cmd */
-	return rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
-}
diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c
index 30f7ca8..81b9c2c 100644
--- a/drivers/mfd/rtsx_pcr.c
+++ b/drivers/mfd/rtsx_pcr.c
@@ -63,6 +63,18 @@ static const struct pci_device_id rtsx_pci_ids[] = {
 
 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
 
+static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
+{
+	rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
+		0xFC, pcr->aspm_en);
+}
+
+static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
+{
+	rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
+		0xFC, 0);
+}
+
 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
 {
 	/* If pci device removed, don't queue idle work any more */
@@ -75,7 +87,7 @@ void rtsx_pci_start_run(struct rtsx_pcr *pcr)
 			pcr->ops->enable_auto_blink(pcr);
 
 		if (pcr->aspm_en)
-			rtsx_pci_write_config_byte(pcr, LCTLR, 0);
+			rtsx_pci_disable_aspm(pcr);
 	}
 
 	mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
@@ -942,7 +954,7 @@ static void rtsx_pci_idle_work(struct work_struct *work)
 		pcr->ops->turn_off_led(pcr);
 
 	if (pcr->aspm_en)
-		rtsx_pci_write_config_byte(pcr, LCTLR, pcr->aspm_en);
+		rtsx_pci_enable_aspm(pcr);
 
 	mutex_unlock(&pcr->pcr_mutex);
 }
@@ -968,6 +980,7 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
 {
 	int err;
 
+	pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
 	rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 
 	rtsx_pci_enable_bus_int(pcr);
@@ -980,6 +993,7 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
 	/* Wait SSC power stable */
 	udelay(200);
 
+	rtsx_pci_disable_aspm(pcr);
 	if (pcr->ops->optimize_phy) {
 		err = pcr->ops->optimize_phy(pcr);
 		if (err < 0)
@@ -1028,10 +1042,8 @@ static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
 	if (err < 0)
 		return err;
 
-	rtsx_pci_write_config_byte(pcr, LCTLR, 0);
-
 	/* Enable clk_request_n to enable clock power management */
-	rtsx_pci_write_config_byte(pcr, 0x81, 1);
+	rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
 	/* Enter L1 when host tx idle */
 	rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
 
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 0103210..33cc63c 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -716,15 +716,6 @@
 
 #define PHY_DUM_REG			0x1F
 
-#define LCTLR				0x80
-#define   LCTLR_EXT_SYNC		0x80
-#define   LCTLR_COMMON_CLOCK_CFG	0x40
-#define   LCTLR_RETRAIN_LINK		0x20
-#define   LCTLR_LINK_DISABLE		0x10
-#define   LCTLR_RCB			0x08
-#define   LCTLR_RESERVED		0x04
-#define   LCTLR_ASPM_CTL_MASK		0x03
-
 #define PCR_SETTING_REG1		0x724
 #define PCR_SETTING_REG2		0x814
 #define PCR_SETTING_REG3		0x747
@@ -759,6 +750,7 @@ enum PDEV_STAT  {PDEV_STAT_IDLE, PDEV_STAT_RUN};
 struct rtsx_pcr {
 	struct pci_dev			*pci;
 	unsigned int			id;
+	int				pcie_cap;
 
 	/* pci resources */
 	unsigned long			addr;
-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A
  2015-01-22  7:30 [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A micky_ching
                   ` (5 preceding siblings ...)
  2015-01-22  7:30 ` [RESEND PATCH v2 6/9] mfd: rtsx: remove LCTLR defination micky_ching
@ 2015-01-22  7:30 ` micky_ching
  2015-02-02  1:07   ` 敬锐
  2015-02-16 14:28   ` Lee Jones
  2015-01-22  7:30 ` [RESEND PATCH v2 8/9] mfd: rtsx: add support for rts525A micky_ching
  2015-01-22  7:30 ` [RESEND PATCH v2 9/9] mfd: rtsx: using pcr_dbg replace dev_dbg micky_ching
  8 siblings, 2 replies; 19+ messages in thread
From: micky_ching @ 2015-01-22  7:30 UTC (permalink / raw)
  To: sameo, lee.jones
  Cc: devel, linux-kernel, gregkh, rogerable, wei_wang, Micky Ching

From: Micky Ching <micky_ching@realsil.com.cn>

add support for new chip rts524A.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
---
 drivers/mfd/rts5249.c        | 186 ++++++++++++++++++++++++++++++++++++-------
 drivers/mfd/rtsx_pcr.c       |  25 +++++-
 drivers/mfd/rtsx_pcr.h       |   7 ++
 include/linux/mfd/rtsx_pci.h | 125 ++++++++++++++++++++++++++++-
 4 files changed, 310 insertions(+), 33 deletions(-)

diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
index 3977946..97dde92 100644
--- a/drivers/mfd/rts5249.c
+++ b/drivers/mfd/rts5249.c
@@ -65,15 +65,17 @@ static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
 			0xFF, driving[drive_sel][2]);
 }
 
-static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
+static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
 {
 	u32 reg;
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
 	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
 
-	if (!rtsx_vendor_setting_valid(reg))
+	if (!rtsx_vendor_setting_valid(reg)) {
+		pcr_dbg(pcr, "skip fetch vendor setting\n");
 		return;
+	}
 
 	pcr->aspm_en = rtsx_reg_to_aspm(reg);
 	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
@@ -87,15 +89,21 @@ static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
 		pcr->flags |= PCR_REVERSE_SOCKET;
 }
 
-static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
+static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
 {
 	/* Set relink_time to 0 */
 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
 
-	if (pm_state == HOST_ENTER_S3)
-		rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
+	if (pm_state == HOST_ENTER_S3) {
+		if (PCI_PID(pcr) == 0x524A)
+			rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
+				D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
+		else if (PCI_PID(pcr) == 0x5249)
+			rtsx_pci_write_register(pcr, PM_CTRL3,
+				D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
+	}
 
 	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
 }
@@ -104,6 +112,8 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
 {
 	rtsx_pci_init_cmd(pcr);
 
+	/* Rest L1SUB Config */
+	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
 	/* Configure GPIO as output */
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 	/* Reset ASPM state to default value */
@@ -189,27 +199,27 @@ static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
 		PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
 }
 
-static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
+static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
 {
 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 }
 
-static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
+static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
 {
 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 }
 
-static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
+static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
 {
 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
 }
 
-static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
+static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
 {
 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
 }
 
-static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
+static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
 {
 	int err;
 
@@ -236,7 +246,7 @@ static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
 	return 0;
 }
 
-static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
+static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
 {
 	rtsx_pci_init_cmd(pcr);
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
@@ -246,22 +256,31 @@ static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
 	return rtsx_pci_send_cmd(pcr, 100);
 }
 
-static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
+static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 {
 	int err;
+	u16 append;
 
-	if (voltage == OUTPUT_3V3) {
-		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
-		if (err < 0)
-			return err;
-	} else if (voltage == OUTPUT_1V8) {
-		err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
+	switch (voltage) {
+	case OUTPUT_3V3:
+		err = rtsx_pci_update_phy(pcr, PHY_TUNE, 0xFC3F, 0x03C0);
 		if (err < 0)
 			return err;
-		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
+		break;
+	case OUTPUT_1V8:
+		append = 0x0100;
+		if (PCI_PID(pcr) == 0x5249) {
+			err = rtsx_pci_update_phy(pcr, PHY_BACR, 0xFFF3, 0);
+			if (err < 0)
+				return err;
+			append = 0x0080;
+		}
+
+		err = rtsx_pci_update_phy(pcr, PHY_TUNE, 0xFC3F, append);
 		if (err < 0)
 			return err;
-	} else {
+		break;
+	default:
 		return -EINVAL;
 	}
 
@@ -272,17 +291,17 @@ static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 }
 
 static const struct pcr_ops rts5249_pcr_ops = {
-	.fetch_vendor_settings = rts5249_fetch_vendor_settings,
+	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
 	.extra_init_hw = rts5249_extra_init_hw,
 	.optimize_phy = rts5249_optimize_phy,
-	.turn_on_led = rts5249_turn_on_led,
-	.turn_off_led = rts5249_turn_off_led,
-	.enable_auto_blink = rts5249_enable_auto_blink,
-	.disable_auto_blink = rts5249_disable_auto_blink,
-	.card_power_on = rts5249_card_power_on,
-	.card_power_off = rts5249_card_power_off,
-	.switch_output_voltage = rts5249_switch_output_voltage,
-	.force_power_down = rts5249_force_power_down,
+	.turn_on_led = rtsx_base_turn_on_led,
+	.turn_off_led = rtsx_base_turn_off_led,
+	.enable_auto_blink = rtsx_base_enable_auto_blink,
+	.disable_auto_blink = rtsx_base_disable_auto_blink,
+	.card_power_on = rtsx_base_card_power_on,
+	.card_power_off = rtsx_base_card_power_off,
+	.switch_output_voltage = rtsx_base_switch_output_voltage,
+	.force_power_down = rtsx_base_force_power_down,
 };
 
 /* SD Pull Control Enable:
@@ -357,3 +376,112 @@ void rts5249_init_params(struct rtsx_pcr *pcr)
 	pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
 	pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
 }
+
+static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
+{
+	addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
+
+	return __rtsx_pci_write_phy_register(pcr, addr, val);
+}
+
+static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
+{
+	addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
+
+	return __rtsx_pci_read_phy_register(pcr, addr, val);
+}
+
+static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
+{
+	int err;
+
+	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
+		D3_DELINK_MODE_EN, 0x00);
+	if (err < 0)
+		return err;
+
+	rtsx_pci_write_phy_register(pcr, PHY_PCR,
+		PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
+		PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
+	rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
+		PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
+
+	if (is_version(pcr, 0x524A, IC_VER_A)) {
+		rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
+			PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
+		rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
+			PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
+			PHY_SSCCR2_TIME2_WIDTH);
+		rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
+			PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
+			PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
+		rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
+			PHY_ANA1D_DEBUG_ADDR);
+		rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
+			PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
+			PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
+			PHY_DIG1E_RCLK_TX_EN_KEEP |
+			PHY_DIG1E_RCLK_TX_TERM_KEEP |
+			PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
+			PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
+			PHY_DIG1E_RX_EN_KEEP);
+	}
+
+	rtsx_pci_write_phy_register(pcr, PHY_ANA08,
+		PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
+		PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
+
+	return 0;
+}
+
+static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
+{
+	rts5249_extra_init_hw(pcr);
+
+	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
+		FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
+	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
+	rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
+		LDO_VCC_LMT_EN);
+	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
+	if (is_version(pcr, 0x524A, IC_VER_A)) {
+		rtsx_pci_write_register(pcr, LDO_DV18_CFG,
+			LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
+		rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
+			LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
+		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
+			LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
+		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
+			LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
+		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
+			LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
+		rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
+			SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
+	}
+
+	return 0;
+}
+
+static const struct pcr_ops rts524a_pcr_ops = {
+	.write_phy = rts524a_write_phy,
+	.read_phy = rts524a_read_phy,
+	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
+	.extra_init_hw = rts524a_extra_init_hw,
+	.optimize_phy = rts524a_optimize_phy,
+	.turn_on_led = rtsx_base_turn_on_led,
+	.turn_off_led = rtsx_base_turn_off_led,
+	.enable_auto_blink = rtsx_base_enable_auto_blink,
+	.disable_auto_blink = rtsx_base_disable_auto_blink,
+	.card_power_on = rtsx_base_card_power_on,
+	.card_power_off = rtsx_base_card_power_off,
+	.switch_output_voltage = rtsx_base_switch_output_voltage,
+	.force_power_down = rtsx_base_force_power_down,
+};
+
+void rts524a_init_params(struct rtsx_pcr *pcr)
+{
+	rts5249_init_params(pcr);
+
+	pcr->ops = &rts524a_pcr_ops;
+}
+
diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c
index 81b9c2c..e6d97ad 100644
--- a/drivers/mfd/rtsx_pcr.c
+++ b/drivers/mfd/rtsx_pcr.c
@@ -58,6 +58,7 @@ static const struct pci_device_id rtsx_pci_ids[] = {
 	{ PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
 	{ PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
 	{ PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
+	{ PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
 	{ 0, }
 };
 
@@ -142,7 +143,7 @@ int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
 }
 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
 
-int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
+int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 {
 	int err, i, finished = 0;
 	u8 tmp;
@@ -174,9 +175,17 @@ int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 
 	return 0;
 }
+
+int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
+{
+	if (pcr->ops->write_phy)
+		return pcr->ops->write_phy(pcr, addr, val);
+
+	return __rtsx_pci_write_phy_register(pcr, addr, val);
+}
 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
 
-int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
+int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 {
 	int err, i, finished = 0;
 	u16 data;
@@ -222,6 +231,14 @@ int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 
 	return 0;
 }
+
+int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
+{
+	if (pcr->ops->read_phy)
+		return pcr->ops->read_phy(pcr, addr, val);
+
+	return __rtsx_pci_read_phy_register(pcr, addr, val);
+}
 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
 
 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
@@ -1093,6 +1110,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
 		rts5249_init_params(pcr);
 		break;
 
+	case 0x524A:
+		rts524a_init_params(pcr);
+		break;
+
 	case 0x5287:
 		rtl8411b_init_params(pcr);
 		break;
diff --git a/drivers/mfd/rtsx_pcr.h b/drivers/mfd/rtsx_pcr.h
index fe2bbb6..e7daf6f 100644
--- a/drivers/mfd/rtsx_pcr.h
+++ b/drivers/mfd/rtsx_pcr.h
@@ -27,12 +27,19 @@
 #define MIN_DIV_N_PCR		80
 #define MAX_DIV_N_PCR		208
 
+#define RTS524A_PME_FORCE_CTL		0xFF78
+#define RTS524A_PM_CTRL3		0xFF7E
+
+int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
+int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
+
 void rts5209_init_params(struct rtsx_pcr *pcr);
 void rts5229_init_params(struct rtsx_pcr *pcr);
 void rtl8411_init_params(struct rtsx_pcr *pcr);
 void rtl8402_init_params(struct rtsx_pcr *pcr);
 void rts5227_init_params(struct rtsx_pcr *pcr);
 void rts5249_init_params(struct rtsx_pcr *pcr);
+void rts524a_init_params(struct rtsx_pcr *pcr);
 void rtl8411b_init_params(struct rtsx_pcr *pcr);
 
 static inline u8 map_sd_drive(int idx)
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 33cc63c..a392546 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -577,8 +577,16 @@
 
 #define CDRESUMECTL			0xFE52
 #define WAKE_SEL_CTL			0xFE54
+#define PCLK_CTL			0xFE55
+#define   PCLK_MODE_SEL			0x20
 #define PME_FORCE_CTL			0xFE56
+
 #define ASPM_FORCE_CTL			0xFE57
+#define   FORCE_ASPM_CTL0		0x10
+#define   FORCE_ASPM_VAL_MASK		0x03
+#define   FORCE_ASPM_L1_EN		0x02
+#define   FORCE_ASPM_L0_EN		0x01
+#define   FORCE_ASPM_NO_ASPM		0x00
 #define PM_CLK_FORCE_CTL		0xFE58
 #define FUNC_FORCE_CTL			0xFE59
 #define PERST_GLITCH_WIDTH		0xFE5C
@@ -590,7 +598,8 @@
 #define   HOST_ENTER_S3			2
 
 #define SDIO_CFG			0xFE70
-
+#define PM_EVENT_DEBUG			0xFE71
+#define   PME_DEBUG_0			0x08
 #define NFTS_TX_CTRL			0xFE72
 
 #define PWR_GATE_CTRL			0xFE75
@@ -602,12 +611,19 @@
 #define PWD_SUSPEND_EN			0xFE76
 #define LDO_PWR_SEL			0xFE78
 
+#define L1SUB_CONFIG1			0xFE8D
+#define L1SUB_CONFIG2			0xFE8E
+#define   L1SUB_AUTO_CFG		0x02
+#define L1SUB_CONFIG3			0xFE8F
+
 #define DUMMY_REG_RESET_0		0xFE90
 
 #define AUTOLOAD_CFG_BASE		0xFF00
 #define PETXCFG				0xFF03
 
 #define PM_CTRL1			0xFF44
+#define   CD_RESUME_EN_MASK		0xF0
+
 #define PM_CTRL2			0xFF45
 #define PM_CTRL3			0xFF46
 #define   SDIO_SEND_PME_EN		0x80
@@ -628,6 +644,61 @@
 #define IMAGE_FLAG_ADDR0		0xCE80
 #define IMAGE_FLAG_ADDR1		0xCE81
 
+#define RREF_CFG			0xFF6C
+#define   RREF_VBGSEL_MASK		0x38
+#define   RREF_VBGSEL_1V25		0x28
+
+#define OOBS_CONFIG			0xFF6E
+#define   OOBS_AUTOK_DIS		0x80
+#define   OOBS_VAL_MASK			0x1F
+
+#define LDO_DV18_CFG			0xFF70
+#define   LDO_DV18_SR_MASK		0xC0
+#define   LDO_DV18_SR_DF		0x40
+
+#define LDO_CONFIG2			0xFF71
+#define   LDO_D3318_MASK		0x07
+#define   LDO_D3318_33V			0x07
+#define   LDO_D3318_18V			0x02
+
+#define LDO_VCC_CFG0			0xFF72
+#define   LDO_VCC_LMTVTH_MASK		0x30
+#define   LDO_VCC_LMTVTH_2A		0x10
+
+#define LDO_VCC_CFG1			0xFF73
+#define   LDO_VCC_REF_TUNE_MASK		0x30
+#define   LDO_VCC_REF_1V2		0x20
+#define   LDO_VCC_TUNE_MASK		0x07
+#define   LDO_VCC_1V8			0x04
+#define   LDO_VCC_3V3			0x07
+#define   LDO_VCC_LMT_EN		0x08
+
+#define LDO_VIO_CFG			0xFF75
+#define   LDO_VIO_SR_MASK		0xC0
+#define   LDO_VIO_SR_DF			0x40
+#define   LDO_VIO_REF_TUNE_MASK		0x30
+#define   LDO_VIO_REF_1V2		0x20
+#define   LDO_VIO_TUNE_MASK		0x07
+#define   LDO_VIO_1V7			0x03
+#define   LDO_VIO_1V8			0x04
+#define   LDO_VIO_3V3			0x07
+
+#define LDO_DV12S_CFG			0xFF76
+#define   LDO_REF12_TUNE_MASK		0x18
+#define   LDO_REF12_TUNE_DF		0x10
+#define   LDO_D12_TUNE_MASK		0x07
+#define   LDO_D12_TUNE_DF		0x04
+
+#define LDO_AV12S_CFG			0xFF77
+#define   LDO_AV12S_TUNE_MASK		0x07
+#define   LDO_AV12S_TUNE_DF		0x04
+
+#define SD40_LDO_CTL1			0xFE7D
+#define   SD40_VIO_TUNE_MASK		0x70
+#define   SD40_VIO_TUNE_1V7		0x30
+#define   SD_VIO_LDO_1V8		0x40
+#define   SD_VIO_LDO_3V3		0x70
+
 /* Phy register */
 #define PHY_PCR				0x00
 #define   PHY_PCR_FORCE_CODE		0xB000
@@ -641,6 +712,10 @@
 #define PHY_RCR1			0x02
 #define   PHY_RCR1_ADP_TIME_4		0x0400
 #define   PHY_RCR1_VCO_COARSE		0x001F
+#define PHY_SSCCR2			0x02
+#define   PHY_SSCCR2_PLL_NCODE		0x0A00
+#define   PHY_SSCCR2_TIME0		0x001C
+#define   PHY_SSCCR2_TIME2_WIDTH	0x0003
 
 #define PHY_RCR2			0x03
 #define   PHY_RCR2_EMPHASE_EN		0x8000
@@ -649,6 +724,9 @@
 #define   PHY_RCR2_FREQSEL_12		0x0040
 #define   PHY_RCR2_CDR_SC_12P		0x0010
 #define   PHY_RCR2_CALIB_LATE		0x0002
+#define PHY_SSCCR3			0x03
+#define   PHY_SSCCR3_STEP_IN		0x2740
+#define   PHY_SSCCR3_CHECK_DELAY	0x0008
 
 #define PHY_RTCR			0x04
 #define PHY_RDR				0x05
@@ -663,6 +741,12 @@
 #define   PHY_TUNE_TUNED18		0x01C0
 #define   PHY_TUNE_TUNED12		0X0020
 #define   PHY_TUNE_TUNEA12		0x0004
+#define PHY_ANA08			0x08
+#define   PHY_ANA08_RX_EQ_DCGAIN	0x5000
+#define   PHY_ANA08_SEL_RX_EN		0x0400
+#define   PHY_ANA08_RX_EQ_VAL		0x03C0
+#define   PHY_ANA08_SCP			0x0020
+#define   PHY_ANA08_SEL_IPI		0x0004
 
 #define PHY_IMR				0x09
 #define PHY_BPCR			0x0A
@@ -698,12 +782,19 @@
 #define   PHY_REV_STOP_CLKWR		0x0004
 
 #define PHY_FLD0			0x1A
+#define PHY_ANA1A			0x1A
+#define   PHY_ANA1A_TXR_LOOPBACK	0x2000
+#define   PHY_ANA1A_RXT_BIST		0x0500
+#define   PHY_ANA1A_TXR_BIST		0x0040
+#define   PHY_ANA1A_REV			0x0006
 #define PHY_FLD1			0x1B
 #define PHY_FLD2			0x1C
 #define PHY_FLD3			0x1D
 #define   PHY_FLD3_TIMER_4		0x0800
 #define   PHY_FLD3_TIMER_6		0x0020
 #define   PHY_FLD3_RXDELINK		0x0004
+#define PHY_ANA1D			0x1D
+#define   PHY_ANA1D_DEBUG_ADDR		0x0004
 
 #define PHY_FLD4			0x1E
 #define   PHY_FLD4_FLDEN_SEL		0x4000
@@ -713,7 +804,18 @@
 #define   PHY_FLD4_BER_COUNT		0x00E0
 #define   PHY_FLD4_BER_TIMER		0x000A
 #define   PHY_FLD4_BER_CHK_EN		0x0001
-
+#define PHY_DIG1E			0x1E
+#define   PHY_DIG1E_REV			0x4000
+#define   PHY_DIG1E_D0_X_D1		0x1000
+#define   PHY_DIG1E_RX_ON_HOST		0x0800
+#define   PHY_DIG1E_RCLK_REF_HOST	0x0400
+#define   PHY_DIG1E_RCLK_TX_EN_KEEP	0x0040
+#define   PHY_DIG1E_RCLK_TX_TERM_KEEP	0x0020
+#define   PHY_DIG1E_RCLK_RX_EIDLE_ON	0x0010
+#define   PHY_DIG1E_TX_TERM_KEEP	0x0008
+#define   PHY_DIG1E_RX_TERM_KEEP	0x0004
+#define   PHY_DIG1E_TX_EN_KEEP		0x0002
+#define   PHY_DIG1E_RX_EN_KEEP		0x0001
 #define PHY_DUM_REG			0x1F
 
 #define PCR_SETTING_REG1		0x724
@@ -729,6 +831,8 @@ struct pcr_handle {
 };
 
 struct pcr_ops {
+	int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
+	int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
 	int		(*extra_init_hw)(struct rtsx_pcr *pcr);
 	int		(*optimize_phy)(struct rtsx_pcr *pcr);
 	int		(*turn_on_led)(struct rtsx_pcr *pcr);
@@ -830,6 +934,10 @@ struct rtsx_pcr {
 #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))
 #define PCI_VID(pcr)			((pcr)->pci->vendor)
 #define PCI_PID(pcr)			((pcr)->pci->device)
+#define is_version(pcr, pid, ver)				\
+	(CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
+#define pcr_dbg(pcr, fmt, arg...)				\
+	dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
 
 #define SDR104_PHASE(val)		((val) & 0xFF)
 #define SDR50_PHASE(val)		(((val) >> 8) & 0xFF)
@@ -899,4 +1007,17 @@ static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
 }
 
+static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
+	u16 mask, u16 append)
+{
+	int err;
+	u16 val;
+
+	err = rtsx_pci_read_phy_register(pcr, addr, &val);
+	if (err < 0)
+		return err;
+
+	return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
+}
+
 #endif
-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [RESEND PATCH v2 8/9] mfd: rtsx: add support for rts525A
  2015-01-22  7:30 [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A micky_ching
                   ` (6 preceding siblings ...)
  2015-01-22  7:30 ` [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A micky_ching
@ 2015-01-22  7:30 ` micky_ching
  2015-02-16 14:37   ` Lee Jones
  2015-01-22  7:30 ` [RESEND PATCH v2 9/9] mfd: rtsx: using pcr_dbg replace dev_dbg micky_ching
  8 siblings, 1 reply; 19+ messages in thread
From: micky_ching @ 2015-01-22  7:30 UTC (permalink / raw)
  To: sameo, lee.jones
  Cc: devel, linux-kernel, gregkh, rogerable, wei_wang, Micky Ching

From: Micky Ching <micky_ching@realsil.com.cn>

add support for new chip rts525A.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
---
 drivers/mfd/rts5249.c        | 104 ++++++++++++++++++++++++++++++++++++++++++-
 drivers/mfd/rtsx_pcr.c       |  13 ++++--
 drivers/mfd/rtsx_pcr.h       |   1 +
 include/linux/mfd/rtsx_pci.h |  15 +++++++
 4 files changed, 129 insertions(+), 4 deletions(-)

diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
index 97dde92..134e03f 100644
--- a/drivers/mfd/rts5249.c
+++ b/drivers/mfd/rts5249.c
@@ -97,7 +97,7 @@ static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
 	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
 
 	if (pm_state == HOST_ENTER_S3) {
-		if (PCI_PID(pcr) == 0x524A)
+		if (PCI_PID(pcr) == 0x524A || PCI_PID(pcr) == 0x525A)
 			rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
 				D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
 		else if (PCI_PID(pcr) == 0x5249)
@@ -485,3 +485,105 @@ void rts524a_init_params(struct rtsx_pcr *pcr)
 	pcr->ops = &rts524a_pcr_ops;
 }
 
+static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card)
+{
+	rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
+		LDO_VCC_TUNE_MASK, LDO_VCC_3V3);
+	return rtsx_base_card_power_on(pcr, card);
+}
+
+static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
+{
+	switch (voltage) {
+	case OUTPUT_3V3:
+		rtsx_pci_write_register(pcr, LDO_CONFIG2,
+			LDO_D3318_MASK, LDO_D3318_33V);
+		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
+		break;
+	case OUTPUT_1V8:
+		rtsx_pci_write_register(pcr, LDO_CONFIG2,
+			LDO_D3318_MASK, LDO_D3318_18V);
+		rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
+			SD_IO_USING_1V8);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	rtsx_pci_init_cmd(pcr);
+	rts5249_fill_driving(pcr, voltage);
+	return rtsx_pci_send_cmd(pcr, 100);
+}
+
+static int rts525a_optimize_phy(struct rtsx_pcr *pcr)
+{
+	int err;
+
+	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
+		D3_DELINK_MODE_EN, 0x00);
+	if (err < 0)
+		return err;
+
+	rtsx_pci_write_phy_register(pcr, _PHY_FLD0,
+		_PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN |
+		_PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT |
+		_PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN);
+
+	rtsx_pci_write_phy_register(pcr, _PHY_ANA03,
+		_PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN |
+		_PHY_CMU_DEBUG_EN);
+
+	if (is_version(pcr, 0x525A, IC_VER_A))
+		rtsx_pci_write_phy_register(pcr, _PHY_REV0,
+			_PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD |
+			_PHY_REV0_CDR_RX_IDLE_BYPASS);
+
+	return 0;
+}
+
+static int rts525a_extra_init_hw(struct rtsx_pcr *pcr)
+{
+	rts5249_extra_init_hw(pcr);
+
+	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
+	if (is_version(pcr, 0x525A, IC_VER_A)) {
+		rtsx_pci_write_register(pcr, L1SUB_CONFIG2,
+			L1SUB_AUTO_CFG, L1SUB_AUTO_CFG);
+		rtsx_pci_write_register(pcr, RREF_CFG,
+			RREF_VBGSEL_MASK, RREF_VBGSEL_1V25);
+		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
+			LDO_VIO_TUNE_MASK, LDO_VIO_1V7);
+		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
+			LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF);
+		rtsx_pci_write_register(pcr, LDO_AV12S_CFG,
+			LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF);
+		rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
+			LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A);
+		rtsx_pci_write_register(pcr, OOBS_CONFIG,
+			OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89);
+	}
+
+	return 0;
+}
+
+static const struct pcr_ops rts525a_pcr_ops = {
+	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
+	.extra_init_hw = rts525a_extra_init_hw,
+	.optimize_phy = rts525a_optimize_phy,
+	.turn_on_led = rtsx_base_turn_on_led,
+	.turn_off_led = rtsx_base_turn_off_led,
+	.enable_auto_blink = rtsx_base_enable_auto_blink,
+	.disable_auto_blink = rtsx_base_disable_auto_blink,
+	.card_power_on = rts525a_card_power_on,
+	.card_power_off = rtsx_base_card_power_off,
+	.switch_output_voltage = rts525a_switch_output_voltage,
+	.force_power_down = rtsx_base_force_power_down,
+};
+
+void rts525a_init_params(struct rtsx_pcr *pcr)
+{
+	rts5249_init_params(pcr);
+
+	pcr->ops = &rts525a_pcr_ops;
+}
+
diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c
index e6d97ad..4c47f94 100644
--- a/drivers/mfd/rtsx_pcr.c
+++ b/drivers/mfd/rtsx_pcr.c
@@ -59,6 +59,7 @@ static const struct pci_device_id rtsx_pci_ids[] = {
 	{ PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
 	{ PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
 	{ PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
+	{ PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
 	{ 0, }
 };
 
@@ -1114,6 +1115,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
 		rts524a_init_params(pcr);
 		break;
 
+	case 0x525A:
+		rts525a_init_params(pcr);
+		break;
+
 	case 0x5287:
 		rtl8411b_init_params(pcr);
 		break;
@@ -1159,7 +1164,7 @@ static int rtsx_pci_probe(struct pci_dev *pcidev,
 	struct rtsx_pcr *pcr;
 	struct pcr_handle *handle;
 	u32 base, len;
-	int ret, i;
+	int ret, i, bar = 0;
 
 	dev_dbg(&(pcidev->dev),
 		": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
@@ -1204,8 +1209,10 @@ static int rtsx_pci_probe(struct pci_dev *pcidev,
 	pcr->pci = pcidev;
 	dev_set_drvdata(&pcidev->dev, handle);
 
-	len = pci_resource_len(pcidev, 0);
-	base = pci_resource_start(pcidev, 0);
+	if (PCI_PID(pcr) == 0x525A)
+		bar = 1;
+	len = pci_resource_len(pcidev, bar);
+	base = pci_resource_start(pcidev, bar);
 	pcr->remap_addr = ioremap_nocache(base, len);
 	if (!pcr->remap_addr) {
 		ret = -ENOMEM;
diff --git a/drivers/mfd/rtsx_pcr.h b/drivers/mfd/rtsx_pcr.h
index e7daf6f..ce48842 100644
--- a/drivers/mfd/rtsx_pcr.h
+++ b/drivers/mfd/rtsx_pcr.h
@@ -40,6 +40,7 @@ void rtl8402_init_params(struct rtsx_pcr *pcr);
 void rts5227_init_params(struct rtsx_pcr *pcr);
 void rts5249_init_params(struct rtsx_pcr *pcr);
 void rts524a_init_params(struct rtsx_pcr *pcr);
+void rts525a_init_params(struct rtsx_pcr *pcr);
 void rtl8411b_init_params(struct rtsx_pcr *pcr);
 
 static inline u8 map_sd_drive(int idx)
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index a392546..c4fb791 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -727,6 +727,10 @@
 #define PHY_SSCCR3			0x03
 #define   PHY_SSCCR3_STEP_IN		0x2740
 #define   PHY_SSCCR3_CHECK_DELAY	0x0008
+#define _PHY_ANA03			0x03
+#define   _PHY_ANA03_TIMER_MAX		0x2700
+#define   _PHY_ANA03_OOBS_DEB_EN	0x0040
+#define   _PHY_CMU_DEBUG_EN		0x0008
 
 #define PHY_RTCR			0x04
 #define PHY_RDR				0x05
@@ -780,6 +784,10 @@
 #define   PHY_REV_STOP_CLKRD		0x0020
 #define   PHY_REV_RX_PWST		0x0008
 #define   PHY_REV_STOP_CLKWR		0x0004
+#define _PHY_REV0			0x19
+#define   _PHY_REV0_FILTER_OUT		0x3800
+#define   _PHY_REV0_CDR_BYPASS_PFD	0x0100
+#define   _PHY_REV0_CDR_RX_IDLE_BYPASS	0x0002
 
 #define PHY_FLD0			0x1A
 #define PHY_ANA1A			0x1A
@@ -795,6 +803,13 @@
 #define   PHY_FLD3_RXDELINK		0x0004
 #define PHY_ANA1D			0x1D
 #define   PHY_ANA1D_DEBUG_ADDR		0x0004
+#define _PHY_FLD0			0x1D
+#define   _PHY_FLD0_CLK_REQ_20C		0x8000
+#define   _PHY_FLD0_RX_IDLE_EN		0x1000
+#define   _PHY_FLD0_BIT_ERR_RSTN	0x0800
+#define   _PHY_FLD0_BER_COUNT		0x01E0
+#define   _PHY_FLD0_BER_TIMER		0x001E
+#define   _PHY_FLD0_CHECK_EN		0x0001
 
 #define PHY_FLD4			0x1E
 #define   PHY_FLD4_FLDEN_SEL		0x4000
-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [RESEND PATCH v2 9/9] mfd: rtsx: using pcr_dbg replace dev_dbg
  2015-01-22  7:30 [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A micky_ching
                   ` (7 preceding siblings ...)
  2015-01-22  7:30 ` [RESEND PATCH v2 8/9] mfd: rtsx: add support for rts525A micky_ching
@ 2015-01-22  7:30 ` micky_ching
  8 siblings, 0 replies; 19+ messages in thread
From: micky_ching @ 2015-01-22  7:30 UTC (permalink / raw)
  To: sameo, lee.jones
  Cc: devel, linux-kernel, gregkh, rogerable, wei_wang, Micky Ching

From: Micky Ching <micky_ching@realsil.com.cn>

pcr_dbg is a wrapper of dev_dbg, which can save some code,
and help to enable/disable debug message static.

Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
Acked-by: Lee Jones <lee.jones@linaro.org>
---
 drivers/mfd/rtl8411.c  | 11 +++++------
 drivers/mfd/rts5209.c  |  4 ++--
 drivers/mfd/rts5227.c  |  4 ++--
 drivers/mfd/rts5229.c  |  4 ++--
 drivers/mfd/rts5249.c  |  4 ++--
 drivers/mfd/rtsx_pcr.c | 49 ++++++++++++++++++++++---------------------------
 6 files changed, 35 insertions(+), 41 deletions(-)

diff --git a/drivers/mfd/rtl8411.c b/drivers/mfd/rtl8411.c
index fdd34c8..b3ae659 100644
--- a/drivers/mfd/rtl8411.c
+++ b/drivers/mfd/rtl8411.c
@@ -53,7 +53,7 @@ static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	u8 reg3 = 0;
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg1);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1);
 
 	if (!rtsx_vendor_setting_valid(reg1))
 		return;
@@ -65,7 +65,7 @@ static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1);
 
 	rtsx_pci_read_config_byte(pcr, PCR_SETTING_REG3, &reg3);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3);
 	pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3);
 }
 
@@ -74,7 +74,7 @@ static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	u32 reg = 0;
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
 
 	if (!rtsx_vendor_setting_valid(reg))
 		return;
@@ -260,9 +260,8 @@ static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr)
 		rtsx_pci_write_register(pcr, CARD_PWR_CTL,
 				BPP_POWER_MASK, BPP_POWER_OFF);
 
-		dev_dbg(&(pcr->pci->dev),
-				"After CD deglitch, card_exist = 0x%x\n",
-				card_exist);
+		pcr_dbg(pcr, "After CD deglitch, card_exist = 0x%x\n",
+			card_exist);
 	}
 
 	if (card_exist & MS_EXIST) {
diff --git a/drivers/mfd/rts5209.c b/drivers/mfd/rts5209.c
index cb04174..373e253 100644
--- a/drivers/mfd/rts5209.c
+++ b/drivers/mfd/rts5209.c
@@ -38,7 +38,7 @@ static void rts5209_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	u32 reg;
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
 
 	if (rts5209_vendor_setting1_valid(reg)) {
 		if (rts5209_reg_check_ms_pmos(reg))
@@ -47,7 +47,7 @@ static void rts5209_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	}
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
 
 	if (rts5209_vendor_setting2_valid(reg)) {
 		pcr->sd30_drive_sel_1v8 =
diff --git a/drivers/mfd/rts5227.c b/drivers/mfd/rts5227.c
index 0c02831..ce012d7 100644
--- a/drivers/mfd/rts5227.c
+++ b/drivers/mfd/rts5227.c
@@ -63,7 +63,7 @@ static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	u32 reg;
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
 
 	if (!rtsx_vendor_setting_valid(reg))
 		return;
@@ -74,7 +74,7 @@ static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
 	if (rtsx_reg_check_reverse_socket(reg))
 		pcr->flags |= PCR_REVERSE_SOCKET;
diff --git a/drivers/mfd/rts5229.c b/drivers/mfd/rts5229.c
index 6353f5d..ace4538 100644
--- a/drivers/mfd/rts5229.c
+++ b/drivers/mfd/rts5229.c
@@ -38,7 +38,7 @@ static void rts5229_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	u32 reg;
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
 
 	if (!rtsx_vendor_setting_valid(reg))
 		return;
@@ -50,7 +50,7 @@ static void rts5229_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
 	pcr->sd30_drive_sel_3v3 =
 		map_sd_drive(rtsx_reg_to_sd30_drive_sel_3v3(reg));
 }
diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
index 134e03f..663d4e3 100644
--- a/drivers/mfd/rts5249.c
+++ b/drivers/mfd/rts5249.c
@@ -70,7 +70,7 @@ static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	u32 reg;
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
 
 	if (!rtsx_vendor_setting_valid(reg)) {
 		pcr_dbg(pcr, "skip fetch vendor setting\n");
@@ -83,7 +83,7 @@ static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
 
 	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
-	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
+	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
 	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
 	if (rtsx_reg_check_reverse_socket(reg))
 		pcr->flags |= PCR_REVERSE_SOCKET;
diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c
index 4c47f94..e11d6fb 100644
--- a/drivers/mfd/rtsx_pcr.c
+++ b/drivers/mfd/rtsx_pcr.c
@@ -316,8 +316,7 @@ int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
 	timeleft = wait_for_completion_interruptible_timeout(
 			&trans_done, msecs_to_jiffies(timeout));
 	if (timeleft <= 0) {
-		dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
-				__func__, __LINE__);
+		pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
 		err = -ETIMEDOUT;
 		goto finish_send_cmd;
 	}
@@ -353,8 +352,7 @@ static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
 	u64 val;
 	u8 option = SG_VALID | SG_TRANS_DATA;
 
-	dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
-			(unsigned int)addr, len);
+	pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
 
 	if (end)
 		option |= SG_END;
@@ -369,11 +367,11 @@ int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 {
 	int err = 0, count;
 
-	dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
+	pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
 	count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
 	if (count < 1)
 		return -EINVAL;
-	dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
+	pcr_dbg(pcr, "DMA mapping count: %d\n", count);
 
 	err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
 
@@ -447,8 +445,7 @@ int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 	timeleft = wait_for_completion_interruptible_timeout(
 			&trans_done, msecs_to_jiffies(timeout));
 	if (timeleft <= 0) {
-		dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
-				__func__, __LINE__);
+		pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
 		err = -ETIMEDOUT;
 		goto out;
 	}
@@ -622,7 +619,7 @@ static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
 	/* Enable Bus Interrupt */
 	rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
 
-	dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
+	pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
 }
 
 static inline u8 double_ssc_depth(u8 depth)
@@ -668,14 +665,13 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 		return err;
 
 	card_clock /= 1000000;
-	dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
+	pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
 
 	clk = card_clock;
 	if (!initial_mode && double_clk)
 		clk = card_clock * 2;
-	dev_dbg(&(pcr->pci->dev),
-			"Internal SSC clock: %dMHz (cur_clock = %d)\n",
-			clk, pcr->cur_clock);
+	pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
+		clk, pcr->cur_clock);
 
 	if (clk == pcr->cur_clock)
 		return 0;
@@ -704,14 +700,14 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 		}
 		div++;
 	}
-	dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
+	pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
 
 	ssc_depth = depth[ssc_depth];
 	if (double_clk)
 		ssc_depth = double_ssc_depth(ssc_depth);
 
 	ssc_depth = revise_ssc_depth(ssc_depth, div);
-	dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
+	pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
 
 	rtsx_pci_init_cmd(pcr);
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
@@ -833,13 +829,13 @@ static void rtsx_pci_card_detect(struct work_struct *work)
 	dwork = to_delayed_work(work);
 	pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
 
-	dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
+	pcr_dbg(pcr, "--> %s\n", __func__);
 
 	mutex_lock(&pcr->pcr_mutex);
 	spin_lock_irqsave(&pcr->lock, flags);
 
 	irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
-	dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
+	pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
 
 	irq_status &= CARD_EXIST;
 	card_inserted = pcr->card_inserted & irq_status;
@@ -850,9 +846,8 @@ static void rtsx_pci_card_detect(struct work_struct *work)
 	spin_unlock_irqrestore(&pcr->lock, flags);
 
 	if (card_inserted || card_removed) {
-		dev_dbg(&(pcr->pci->dev),
-				"card_inserted: 0x%x, card_removed: 0x%x\n",
-				card_inserted, card_removed);
+		pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
+			card_inserted, card_removed);
 
 		if (pcr->ops->cd_deglitch)
 			card_inserted = pcr->ops->cd_deglitch(pcr);
@@ -960,7 +955,7 @@ static void rtsx_pci_idle_work(struct work_struct *work)
 	struct delayed_work *dwork = to_delayed_work(work);
 	struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
 
-	dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
+	pcr_dbg(pcr, "--> %s\n", __func__);
 
 	mutex_lock(&pcr->pcr_mutex);
 
@@ -1128,7 +1123,7 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
 		break;
 	}
 
-	dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
+	pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
 			PCI_PID(pcr), pcr->ic_version);
 
 	pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
@@ -1139,14 +1134,14 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
 	if (pcr->ops->fetch_vendor_settings)
 		pcr->ops->fetch_vendor_settings(pcr);
 
-	dev_dbg(&(pcr->pci->dev), "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
-	dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_1v8 = 0x%x\n",
+	pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
+	pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
 			pcr->sd30_drive_sel_1v8);
-	dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_3v3 = 0x%x\n",
+	pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
 			pcr->sd30_drive_sel_3v3);
-	dev_dbg(&(pcr->pci->dev), "pcr->card_drive_sel = 0x%x\n",
+	pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
 			pcr->card_drive_sel);
-	dev_dbg(&(pcr->pci->dev), "pcr->flags = 0x%x\n", pcr->flags);
+	pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
 
 	pcr->state = PDEV_STAT_IDLE;
 	err = rtsx_pci_init_hw(pcr);
-- 
1.9.1


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [RESEND PATCH v2 4/9] mfd: rtsx: update driving settings
  2015-01-22  7:30 ` [RESEND PATCH v2 4/9] mfd: rtsx: update driving settings micky_ching
@ 2015-01-22  7:40   ` Joe Perches
  0 siblings, 0 replies; 19+ messages in thread
From: Joe Perches @ 2015-01-22  7:40 UTC (permalink / raw)
  To: micky_ching
  Cc: sameo, lee.jones, devel, linux-kernel, gregkh, rogerable, wei_wang

On Thu, 2015-01-22 at 15:30 +0800, micky_ching@realsil.com.cn wrote:
> update card drive settings, This setting can be used for rts5249
> rts524A and rts525A.
[]
> diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c

> @@ -36,16 +36,16 @@ static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
>  static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
>  {
>  	u8 driving_3v3[4][3] = {

It'd be nice to make these arrays static const

> -		{0x11, 0x11, 0x11},
> +		{0x11, 0x11, 0x18},
>  		{0x55, 0x55, 0x5C},
> -		{0x99, 0x99, 0x92},
> -		{0x99, 0x99, 0x92},
> +		{0xFF, 0xFF, 0xFF},
> +		{0x96, 0x96, 0x96},
>  	};
>  	u8 driving_1v8[4][3] = {
> +		{0xC4, 0xC4, 0xC4},
>  		{0x3C, 0x3C, 0x3C},
> -		{0xB3, 0xB3, 0xB3},
>  		{0xFE, 0xFE, 0xFE},
> -		{0xC4, 0xC4, 0xC4},
> +		{0xB3, 0xB3, 0xB3},
>  	};
>  	u8 (*driving)[3], drive_sel;



^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A
  2015-01-22  7:30 ` [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A micky_ching
@ 2015-02-02  1:07   ` 敬锐
  2015-02-02  8:52     ` Lee Jones
  2015-02-16 14:28   ` Lee Jones
  1 sibling, 1 reply; 19+ messages in thread
From: 敬锐 @ 2015-02-02  1:07 UTC (permalink / raw)
  To: sameo, lee.jones; +Cc: devel, linux-kernel, gregkh, rogerable, 王炜

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="gb2312", Size: 21046 bytes --]

Hi Lee,

do you have reviewed this patchset?

regards.
micky.
On 01/22/2015 03:30 PM, micky_ching@realsil.com.cn wrote:
> From: Micky Ching <micky_ching@realsil.com.cn>
>
> add support for new chip rts524A.
>
> Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
> ---
>   drivers/mfd/rts5249.c        | 186 ++++++++++++++++++++++++++++++++++++-------
>   drivers/mfd/rtsx_pcr.c       |  25 +++++-
>   drivers/mfd/rtsx_pcr.h       |   7 ++
>   include/linux/mfd/rtsx_pci.h | 125 ++++++++++++++++++++++++++++-
>   4 files changed, 310 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
> index 3977946..97dde92 100644
> --- a/drivers/mfd/rts5249.c
> +++ b/drivers/mfd/rts5249.c
> @@ -65,15 +65,17 @@ static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
>   			0xFF, driving[drive_sel][2]);
>   }
>   
> -static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
> +static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
>   {
>   	u32 reg;
>   
>   	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
>   	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
>   
> -	if (!rtsx_vendor_setting_valid(reg))
> +	if (!rtsx_vendor_setting_valid(reg)) {
> +		pcr_dbg(pcr, "skip fetch vendor setting\n");
>   		return;
> +	}
>   
>   	pcr->aspm_en = rtsx_reg_to_aspm(reg);
>   	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
> @@ -87,15 +89,21 @@ static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
>   		pcr->flags |= PCR_REVERSE_SOCKET;
>   }
>   
> -static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
> +static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
>   {
>   	/* Set relink_time to 0 */
>   	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
>   	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
>   	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
>   
> -	if (pm_state == HOST_ENTER_S3)
> -		rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
> +	if (pm_state == HOST_ENTER_S3) {
> +		if (PCI_PID(pcr) == 0x524A)
> +			rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
> +				D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
> +		else if (PCI_PID(pcr) == 0x5249)
> +			rtsx_pci_write_register(pcr, PM_CTRL3,
> +				D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
> +	}
>   
>   	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
>   }
> @@ -104,6 +112,8 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
>   {
>   	rtsx_pci_init_cmd(pcr);
>   
> +	/* Rest L1SUB Config */
> +	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
>   	/* Configure GPIO as output */
>   	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
>   	/* Reset ASPM state to default value */
> @@ -189,27 +199,27 @@ static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
>   		PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
>   }
>   
> -static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
> +static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
>   {
>   	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
>   }
>   
> -static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
> +static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
>   {
>   	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
>   }
>   
> -static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
> +static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
>   {
>   	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
>   }
>   
> -static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
> +static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
>   {
>   	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
>   }
>   
> -static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
> +static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
>   {
>   	int err;
>   
> @@ -236,7 +246,7 @@ static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
>   	return 0;
>   }
>   
> -static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
> +static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
>   {
>   	rtsx_pci_init_cmd(pcr);
>   	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
> @@ -246,22 +256,31 @@ static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
>   	return rtsx_pci_send_cmd(pcr, 100);
>   }
>   
> -static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
> +static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
>   {
>   	int err;
> +	u16 append;
>   
> -	if (voltage == OUTPUT_3V3) {
> -		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
> -		if (err < 0)
> -			return err;
> -	} else if (voltage == OUTPUT_1V8) {
> -		err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
> +	switch (voltage) {
> +	case OUTPUT_3V3:
> +		err = rtsx_pci_update_phy(pcr, PHY_TUNE, 0xFC3F, 0x03C0);
>   		if (err < 0)
>   			return err;
> -		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
> +		break;
> +	case OUTPUT_1V8:
> +		append = 0x0100;
> +		if (PCI_PID(pcr) == 0x5249) {
> +			err = rtsx_pci_update_phy(pcr, PHY_BACR, 0xFFF3, 0);
> +			if (err < 0)
> +				return err;
> +			append = 0x0080;
> +		}
> +
> +		err = rtsx_pci_update_phy(pcr, PHY_TUNE, 0xFC3F, append);
>   		if (err < 0)
>   			return err;
> -	} else {
> +		break;
> +	default:
>   		return -EINVAL;
>   	}
>   
> @@ -272,17 +291,17 @@ static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
>   }
>   
>   static const struct pcr_ops rts5249_pcr_ops = {
> -	.fetch_vendor_settings = rts5249_fetch_vendor_settings,
> +	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
>   	.extra_init_hw = rts5249_extra_init_hw,
>   	.optimize_phy = rts5249_optimize_phy,
> -	.turn_on_led = rts5249_turn_on_led,
> -	.turn_off_led = rts5249_turn_off_led,
> -	.enable_auto_blink = rts5249_enable_auto_blink,
> -	.disable_auto_blink = rts5249_disable_auto_blink,
> -	.card_power_on = rts5249_card_power_on,
> -	.card_power_off = rts5249_card_power_off,
> -	.switch_output_voltage = rts5249_switch_output_voltage,
> -	.force_power_down = rts5249_force_power_down,
> +	.turn_on_led = rtsx_base_turn_on_led,
> +	.turn_off_led = rtsx_base_turn_off_led,
> +	.enable_auto_blink = rtsx_base_enable_auto_blink,
> +	.disable_auto_blink = rtsx_base_disable_auto_blink,
> +	.card_power_on = rtsx_base_card_power_on,
> +	.card_power_off = rtsx_base_card_power_off,
> +	.switch_output_voltage = rtsx_base_switch_output_voltage,
> +	.force_power_down = rtsx_base_force_power_down,
>   };
>   
>   /* SD Pull Control Enable:
> @@ -357,3 +376,112 @@ void rts5249_init_params(struct rtsx_pcr *pcr)
>   	pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
>   	pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
>   }
> +
> +static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
> +{
> +	addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
> +
> +	return __rtsx_pci_write_phy_register(pcr, addr, val);
> +}
> +
> +static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> +{
> +	addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
> +
> +	return __rtsx_pci_read_phy_register(pcr, addr, val);
> +}
> +
> +static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
> +{
> +	int err;
> +
> +	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
> +		D3_DELINK_MODE_EN, 0x00);
> +	if (err < 0)
> +		return err;
> +
> +	rtsx_pci_write_phy_register(pcr, PHY_PCR,
> +		PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
> +		PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
> +	rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
> +		PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
> +
> +	if (is_version(pcr, 0x524A, IC_VER_A)) {
> +		rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
> +			PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
> +		rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
> +			PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
> +			PHY_SSCCR2_TIME2_WIDTH);
> +		rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
> +			PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
> +			PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
> +		rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
> +			PHY_ANA1D_DEBUG_ADDR);
> +		rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
> +			PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
> +			PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
> +			PHY_DIG1E_RCLK_TX_EN_KEEP |
> +			PHY_DIG1E_RCLK_TX_TERM_KEEP |
> +			PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
> +			PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
> +			PHY_DIG1E_RX_EN_KEEP);
> +	}
> +
> +	rtsx_pci_write_phy_register(pcr, PHY_ANA08,
> +		PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
> +		PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
> +
> +	return 0;
> +}
> +
> +static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
> +{
> +	rts5249_extra_init_hw(pcr);
> +
> +	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
> +		FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
> +	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
> +	rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
> +		LDO_VCC_LMT_EN);
> +	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
> +	if (is_version(pcr, 0x524A, IC_VER_A)) {
> +		rtsx_pci_write_register(pcr, LDO_DV18_CFG,
> +			LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
> +		rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
> +			LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
> +		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
> +			LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
> +		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
> +			LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
> +		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
> +			LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
> +		rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
> +			SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct pcr_ops rts524a_pcr_ops = {
> +	.write_phy = rts524a_write_phy,
> +	.read_phy = rts524a_read_phy,
> +	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
> +	.extra_init_hw = rts524a_extra_init_hw,
> +	.optimize_phy = rts524a_optimize_phy,
> +	.turn_on_led = rtsx_base_turn_on_led,
> +	.turn_off_led = rtsx_base_turn_off_led,
> +	.enable_auto_blink = rtsx_base_enable_auto_blink,
> +	.disable_auto_blink = rtsx_base_disable_auto_blink,
> +	.card_power_on = rtsx_base_card_power_on,
> +	.card_power_off = rtsx_base_card_power_off,
> +	.switch_output_voltage = rtsx_base_switch_output_voltage,
> +	.force_power_down = rtsx_base_force_power_down,
> +};
> +
> +void rts524a_init_params(struct rtsx_pcr *pcr)
> +{
> +	rts5249_init_params(pcr);
> +
> +	pcr->ops = &rts524a_pcr_ops;
> +}
> +
> diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c
> index 81b9c2c..e6d97ad 100644
> --- a/drivers/mfd/rtsx_pcr.c
> +++ b/drivers/mfd/rtsx_pcr.c
> @@ -58,6 +58,7 @@ static const struct pci_device_id rtsx_pci_ids[] = {
>   	{ PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
>   	{ PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
>   	{ PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
> +	{ PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
>   	{ 0, }
>   };
>   
> @@ -142,7 +143,7 @@ int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
>   }
>   EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
>   
> -int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
> +int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
>   {
>   	int err, i, finished = 0;
>   	u8 tmp;
> @@ -174,9 +175,17 @@ int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
>   
>   	return 0;
>   }
> +
> +int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
> +{
> +	if (pcr->ops->write_phy)
> +		return pcr->ops->write_phy(pcr, addr, val);
> +
> +	return __rtsx_pci_write_phy_register(pcr, addr, val);
> +}
>   EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
>   
> -int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> +int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
>   {
>   	int err, i, finished = 0;
>   	u16 data;
> @@ -222,6 +231,14 @@ int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
>   
>   	return 0;
>   }
> +
> +int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> +{
> +	if (pcr->ops->read_phy)
> +		return pcr->ops->read_phy(pcr, addr, val);
> +
> +	return __rtsx_pci_read_phy_register(pcr, addr, val);
> +}
>   EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
>   
>   void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
> @@ -1093,6 +1110,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
>   		rts5249_init_params(pcr);
>   		break;
>   
> +	case 0x524A:
> +		rts524a_init_params(pcr);
> +		break;
> +
>   	case 0x5287:
>   		rtl8411b_init_params(pcr);
>   		break;
> diff --git a/drivers/mfd/rtsx_pcr.h b/drivers/mfd/rtsx_pcr.h
> index fe2bbb6..e7daf6f 100644
> --- a/drivers/mfd/rtsx_pcr.h
> +++ b/drivers/mfd/rtsx_pcr.h
> @@ -27,12 +27,19 @@
>   #define MIN_DIV_N_PCR		80
>   #define MAX_DIV_N_PCR		208
>   
> +#define RTS524A_PME_FORCE_CTL		0xFF78
> +#define RTS524A_PM_CTRL3		0xFF7E
> +
> +int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
> +int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
> +
>   void rts5209_init_params(struct rtsx_pcr *pcr);
>   void rts5229_init_params(struct rtsx_pcr *pcr);
>   void rtl8411_init_params(struct rtsx_pcr *pcr);
>   void rtl8402_init_params(struct rtsx_pcr *pcr);
>   void rts5227_init_params(struct rtsx_pcr *pcr);
>   void rts5249_init_params(struct rtsx_pcr *pcr);
> +void rts524a_init_params(struct rtsx_pcr *pcr);
>   void rtl8411b_init_params(struct rtsx_pcr *pcr);
>   
>   static inline u8 map_sd_drive(int idx)
> diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
> index 33cc63c..a392546 100644
> --- a/include/linux/mfd/rtsx_pci.h
> +++ b/include/linux/mfd/rtsx_pci.h
> @@ -577,8 +577,16 @@
>   
>   #define CDRESUMECTL			0xFE52
>   #define WAKE_SEL_CTL			0xFE54
> +#define PCLK_CTL			0xFE55
> +#define   PCLK_MODE_SEL			0x20
>   #define PME_FORCE_CTL			0xFE56
> +
>   #define ASPM_FORCE_CTL			0xFE57
> +#define   FORCE_ASPM_CTL0		0x10
> +#define   FORCE_ASPM_VAL_MASK		0x03
> +#define   FORCE_ASPM_L1_EN		0x02
> +#define   FORCE_ASPM_L0_EN		0x01
> +#define   FORCE_ASPM_NO_ASPM		0x00
>   #define PM_CLK_FORCE_CTL		0xFE58
>   #define FUNC_FORCE_CTL			0xFE59
>   #define PERST_GLITCH_WIDTH		0xFE5C
> @@ -590,7 +598,8 @@
>   #define   HOST_ENTER_S3			2
>   
>   #define SDIO_CFG			0xFE70
> -
> +#define PM_EVENT_DEBUG			0xFE71
> +#define   PME_DEBUG_0			0x08
>   #define NFTS_TX_CTRL			0xFE72
>   
>   #define PWR_GATE_CTRL			0xFE75
> @@ -602,12 +611,19 @@
>   #define PWD_SUSPEND_EN			0xFE76
>   #define LDO_PWR_SEL			0xFE78
>   
> +#define L1SUB_CONFIG1			0xFE8D
> +#define L1SUB_CONFIG2			0xFE8E
> +#define   L1SUB_AUTO_CFG		0x02
> +#define L1SUB_CONFIG3			0xFE8F
> +
>   #define DUMMY_REG_RESET_0		0xFE90
>   
>   #define AUTOLOAD_CFG_BASE		0xFF00
>   #define PETXCFG				0xFF03
>   
>   #define PM_CTRL1			0xFF44
> +#define   CD_RESUME_EN_MASK		0xF0
> +
>   #define PM_CTRL2			0xFF45
>   #define PM_CTRL3			0xFF46
>   #define   SDIO_SEND_PME_EN		0x80
> @@ -628,6 +644,61 @@
>   #define IMAGE_FLAG_ADDR0		0xCE80
>   #define IMAGE_FLAG_ADDR1		0xCE81
>   
> +#define RREF_CFG			0xFF6C
> +#define   RREF_VBGSEL_MASK		0x38
> +#define   RREF_VBGSEL_1V25		0x28
> +
> +#define OOBS_CONFIG			0xFF6E
> +#define   OOBS_AUTOK_DIS		0x80
> +#define   OOBS_VAL_MASK			0x1F
> +
> +#define LDO_DV18_CFG			0xFF70
> +#define   LDO_DV18_SR_MASK		0xC0
> +#define   LDO_DV18_SR_DF		0x40
> +
> +#define LDO_CONFIG2			0xFF71
> +#define   LDO_D3318_MASK		0x07
> +#define   LDO_D3318_33V			0x07
> +#define   LDO_D3318_18V			0x02
> +
> +#define LDO_VCC_CFG0			0xFF72
> +#define   LDO_VCC_LMTVTH_MASK		0x30
> +#define   LDO_VCC_LMTVTH_2A		0x10
> +
> +#define LDO_VCC_CFG1			0xFF73
> +#define   LDO_VCC_REF_TUNE_MASK		0x30
> +#define   LDO_VCC_REF_1V2		0x20
> +#define   LDO_VCC_TUNE_MASK		0x07
> +#define   LDO_VCC_1V8			0x04
> +#define   LDO_VCC_3V3			0x07
> +#define   LDO_VCC_LMT_EN		0x08
> +
> +#define LDO_VIO_CFG			0xFF75
> +#define   LDO_VIO_SR_MASK		0xC0
> +#define   LDO_VIO_SR_DF			0x40
> +#define   LDO_VIO_REF_TUNE_MASK		0x30
> +#define   LDO_VIO_REF_1V2		0x20
> +#define   LDO_VIO_TUNE_MASK		0x07
> +#define   LDO_VIO_1V7			0x03
> +#define   LDO_VIO_1V8			0x04
> +#define   LDO_VIO_3V3			0x07
> +
> +#define LDO_DV12S_CFG			0xFF76
> +#define   LDO_REF12_TUNE_MASK		0x18
> +#define   LDO_REF12_TUNE_DF		0x10
> +#define   LDO_D12_TUNE_MASK		0x07
> +#define   LDO_D12_TUNE_DF		0x04
> +
> +#define LDO_AV12S_CFG			0xFF77
> +#define   LDO_AV12S_TUNE_MASK		0x07
> +#define   LDO_AV12S_TUNE_DF		0x04
> +
> +#define SD40_LDO_CTL1			0xFE7D
> +#define   SD40_VIO_TUNE_MASK		0x70
> +#define   SD40_VIO_TUNE_1V7		0x30
> +#define   SD_VIO_LDO_1V8		0x40
> +#define   SD_VIO_LDO_3V3		0x70
> +
>   /* Phy register */
>   #define PHY_PCR				0x00
>   #define   PHY_PCR_FORCE_CODE		0xB000
> @@ -641,6 +712,10 @@
>   #define PHY_RCR1			0x02
>   #define   PHY_RCR1_ADP_TIME_4		0x0400
>   #define   PHY_RCR1_VCO_COARSE		0x001F
> +#define PHY_SSCCR2			0x02
> +#define   PHY_SSCCR2_PLL_NCODE		0x0A00
> +#define   PHY_SSCCR2_TIME0		0x001C
> +#define   PHY_SSCCR2_TIME2_WIDTH	0x0003
>   
>   #define PHY_RCR2			0x03
>   #define   PHY_RCR2_EMPHASE_EN		0x8000
> @@ -649,6 +724,9 @@
>   #define   PHY_RCR2_FREQSEL_12		0x0040
>   #define   PHY_RCR2_CDR_SC_12P		0x0010
>   #define   PHY_RCR2_CALIB_LATE		0x0002
> +#define PHY_SSCCR3			0x03
> +#define   PHY_SSCCR3_STEP_IN		0x2740
> +#define   PHY_SSCCR3_CHECK_DELAY	0x0008
>   
>   #define PHY_RTCR			0x04
>   #define PHY_RDR				0x05
> @@ -663,6 +741,12 @@
>   #define   PHY_TUNE_TUNED18		0x01C0
>   #define   PHY_TUNE_TUNED12		0X0020
>   #define   PHY_TUNE_TUNEA12		0x0004
> +#define PHY_ANA08			0x08
> +#define   PHY_ANA08_RX_EQ_DCGAIN	0x5000
> +#define   PHY_ANA08_SEL_RX_EN		0x0400
> +#define   PHY_ANA08_RX_EQ_VAL		0x03C0
> +#define   PHY_ANA08_SCP			0x0020
> +#define   PHY_ANA08_SEL_IPI		0x0004
>   
>   #define PHY_IMR				0x09
>   #define PHY_BPCR			0x0A
> @@ -698,12 +782,19 @@
>   #define   PHY_REV_STOP_CLKWR		0x0004
>   
>   #define PHY_FLD0			0x1A
> +#define PHY_ANA1A			0x1A
> +#define   PHY_ANA1A_TXR_LOOPBACK	0x2000
> +#define   PHY_ANA1A_RXT_BIST		0x0500
> +#define   PHY_ANA1A_TXR_BIST		0x0040
> +#define   PHY_ANA1A_REV			0x0006
>   #define PHY_FLD1			0x1B
>   #define PHY_FLD2			0x1C
>   #define PHY_FLD3			0x1D
>   #define   PHY_FLD3_TIMER_4		0x0800
>   #define   PHY_FLD3_TIMER_6		0x0020
>   #define   PHY_FLD3_RXDELINK		0x0004
> +#define PHY_ANA1D			0x1D
> +#define   PHY_ANA1D_DEBUG_ADDR		0x0004
>   
>   #define PHY_FLD4			0x1E
>   #define   PHY_FLD4_FLDEN_SEL		0x4000
> @@ -713,7 +804,18 @@
>   #define   PHY_FLD4_BER_COUNT		0x00E0
>   #define   PHY_FLD4_BER_TIMER		0x000A
>   #define   PHY_FLD4_BER_CHK_EN		0x0001
> -
> +#define PHY_DIG1E			0x1E
> +#define   PHY_DIG1E_REV			0x4000
> +#define   PHY_DIG1E_D0_X_D1		0x1000
> +#define   PHY_DIG1E_RX_ON_HOST		0x0800
> +#define   PHY_DIG1E_RCLK_REF_HOST	0x0400
> +#define   PHY_DIG1E_RCLK_TX_EN_KEEP	0x0040
> +#define   PHY_DIG1E_RCLK_TX_TERM_KEEP	0x0020
> +#define   PHY_DIG1E_RCLK_RX_EIDLE_ON	0x0010
> +#define   PHY_DIG1E_TX_TERM_KEEP	0x0008
> +#define   PHY_DIG1E_RX_TERM_KEEP	0x0004
> +#define   PHY_DIG1E_TX_EN_KEEP		0x0002
> +#define   PHY_DIG1E_RX_EN_KEEP		0x0001
>   #define PHY_DUM_REG			0x1F
>   
>   #define PCR_SETTING_REG1		0x724
> @@ -729,6 +831,8 @@ struct pcr_handle {
>   };
>   
>   struct pcr_ops {
> +	int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
> +	int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
>   	int		(*extra_init_hw)(struct rtsx_pcr *pcr);
>   	int		(*optimize_phy)(struct rtsx_pcr *pcr);
>   	int		(*turn_on_led)(struct rtsx_pcr *pcr);
> @@ -830,6 +934,10 @@ struct rtsx_pcr {
>   #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))
>   #define PCI_VID(pcr)			((pcr)->pci->vendor)
>   #define PCI_PID(pcr)			((pcr)->pci->device)
> +#define is_version(pcr, pid, ver)				\
> +	(CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
> +#define pcr_dbg(pcr, fmt, arg...)				\
> +	dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
>   
>   #define SDR104_PHASE(val)		((val) & 0xFF)
>   #define SDR50_PHASE(val)		(((val) >> 8) & 0xFF)
> @@ -899,4 +1007,17 @@ static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
>   	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
>   }
>   
> +static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
> +	u16 mask, u16 append)
> +{
> +	int err;
> +	u16 val;
> +
> +	err = rtsx_pci_read_phy_register(pcr, addr, &val);
> +	if (err < 0)
> +		return err;
> +
> +	return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
> +}
> +
>   #endif
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A
  2015-02-02  1:07   ` 敬锐
@ 2015-02-02  8:52     ` Lee Jones
  0 siblings, 0 replies; 19+ messages in thread
From: Lee Jones @ 2015-02-02  8:52 UTC (permalink / raw)
  To: 敬锐
  Cc: sameo, devel, linux-kernel, gregkh, rogerable, 王炜

> do you have reviewed this patchset?

Yes, but ...

a) You only sent it 7 working days ago -- give me a chance
b) We are already at -rc7, so I have stopped accepting patches
c) I currently have my head buried under a tonne of my own work

... so please don't nag -- you're beginning to sound like my Mrs! ;)

> On 01/22/2015 03:30 PM, micky_ching@realsil.com.cn wrote:
> > From: Micky Ching <micky_ching@realsil.com.cn>
> >
> > add support for new chip rts524A.
> >
> > Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
> > ---
> >   drivers/mfd/rts5249.c        | 186 ++++++++++++++++++++++++++++++++++++-------
> >   drivers/mfd/rtsx_pcr.c       |  25 +++++-
> >   drivers/mfd/rtsx_pcr.h       |   7 ++
> >   include/linux/mfd/rtsx_pci.h | 125 ++++++++++++++++++++++++++++-
> >   4 files changed, 310 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
> > index 3977946..97dde92 100644
> > --- a/drivers/mfd/rts5249.c
> > +++ b/drivers/mfd/rts5249.c
> > @@ -65,15 +65,17 @@ static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
> >   			0xFF, driving[drive_sel][2]);
> >   }
> >   
> > -static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
> > +static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
> >   {
> >   	u32 reg;
> >   
> >   	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
> >   	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
> >   
> > -	if (!rtsx_vendor_setting_valid(reg))
> > +	if (!rtsx_vendor_setting_valid(reg)) {
> > +		pcr_dbg(pcr, "skip fetch vendor setting\n");
> >   		return;
> > +	}
> >   
> >   	pcr->aspm_en = rtsx_reg_to_aspm(reg);
> >   	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
> > @@ -87,15 +89,21 @@ static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
> >   		pcr->flags |= PCR_REVERSE_SOCKET;
> >   }
> >   
> > -static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
> > +static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
> >   {
> >   	/* Set relink_time to 0 */
> >   	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
> >   	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
> >   	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
> >   
> > -	if (pm_state == HOST_ENTER_S3)
> > -		rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
> > +	if (pm_state == HOST_ENTER_S3) {
> > +		if (PCI_PID(pcr) == 0x524A)
> > +			rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
> > +				D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
> > +		else if (PCI_PID(pcr) == 0x5249)
> > +			rtsx_pci_write_register(pcr, PM_CTRL3,
> > +				D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
> > +	}
> >   
> >   	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
> >   }
> > @@ -104,6 +112,8 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
> >   {
> >   	rtsx_pci_init_cmd(pcr);
> >   
> > +	/* Rest L1SUB Config */
> > +	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
> >   	/* Configure GPIO as output */
> >   	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
> >   	/* Reset ASPM state to default value */
> > @@ -189,27 +199,27 @@ static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
> >   		PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
> >   }
> >   
> > -static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
> > +static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
> >   {
> >   	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
> >   }
> >   
> > -static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
> > +static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
> >   {
> >   	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
> >   }
> >   
> > -static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
> > +static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
> >   {
> >   	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
> >   }
> >   
> > -static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
> > +static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
> >   {
> >   	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
> >   }
> >   
> > -static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
> > +static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
> >   {
> >   	int err;
> >   
> > @@ -236,7 +246,7 @@ static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
> >   	return 0;
> >   }
> >   
> > -static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
> > +static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
> >   {
> >   	rtsx_pci_init_cmd(pcr);
> >   	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
> > @@ -246,22 +256,31 @@ static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
> >   	return rtsx_pci_send_cmd(pcr, 100);
> >   }
> >   
> > -static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
> > +static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
> >   {
> >   	int err;
> > +	u16 append;
> >   
> > -	if (voltage == OUTPUT_3V3) {
> > -		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
> > -		if (err < 0)
> > -			return err;
> > -	} else if (voltage == OUTPUT_1V8) {
> > -		err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
> > +	switch (voltage) {
> > +	case OUTPUT_3V3:
> > +		err = rtsx_pci_update_phy(pcr, PHY_TUNE, 0xFC3F, 0x03C0);
> >   		if (err < 0)
> >   			return err;
> > -		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
> > +		break;
> > +	case OUTPUT_1V8:
> > +		append = 0x0100;
> > +		if (PCI_PID(pcr) == 0x5249) {
> > +			err = rtsx_pci_update_phy(pcr, PHY_BACR, 0xFFF3, 0);
> > +			if (err < 0)
> > +				return err;
> > +			append = 0x0080;
> > +		}
> > +
> > +		err = rtsx_pci_update_phy(pcr, PHY_TUNE, 0xFC3F, append);
> >   		if (err < 0)
> >   			return err;
> > -	} else {
> > +		break;
> > +	default:
> >   		return -EINVAL;
> >   	}
> >   
> > @@ -272,17 +291,17 @@ static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
> >   }
> >   
> >   static const struct pcr_ops rts5249_pcr_ops = {
> > -	.fetch_vendor_settings = rts5249_fetch_vendor_settings,
> > +	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
> >   	.extra_init_hw = rts5249_extra_init_hw,
> >   	.optimize_phy = rts5249_optimize_phy,
> > -	.turn_on_led = rts5249_turn_on_led,
> > -	.turn_off_led = rts5249_turn_off_led,
> > -	.enable_auto_blink = rts5249_enable_auto_blink,
> > -	.disable_auto_blink = rts5249_disable_auto_blink,
> > -	.card_power_on = rts5249_card_power_on,
> > -	.card_power_off = rts5249_card_power_off,
> > -	.switch_output_voltage = rts5249_switch_output_voltage,
> > -	.force_power_down = rts5249_force_power_down,
> > +	.turn_on_led = rtsx_base_turn_on_led,
> > +	.turn_off_led = rtsx_base_turn_off_led,
> > +	.enable_auto_blink = rtsx_base_enable_auto_blink,
> > +	.disable_auto_blink = rtsx_base_disable_auto_blink,
> > +	.card_power_on = rtsx_base_card_power_on,
> > +	.card_power_off = rtsx_base_card_power_off,
> > +	.switch_output_voltage = rtsx_base_switch_output_voltage,
> > +	.force_power_down = rtsx_base_force_power_down,
> >   };
> >   
> >   /* SD Pull Control Enable:
> > @@ -357,3 +376,112 @@ void rts5249_init_params(struct rtsx_pcr *pcr)
> >   	pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
> >   	pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
> >   }
> > +
> > +static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
> > +{
> > +	addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
> > +
> > +	return __rtsx_pci_write_phy_register(pcr, addr, val);
> > +}
> > +
> > +static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> > +{
> > +	addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
> > +
> > +	return __rtsx_pci_read_phy_register(pcr, addr, val);
> > +}
> > +
> > +static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
> > +{
> > +	int err;
> > +
> > +	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
> > +		D3_DELINK_MODE_EN, 0x00);
> > +	if (err < 0)
> > +		return err;
> > +
> > +	rtsx_pci_write_phy_register(pcr, PHY_PCR,
> > +		PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
> > +		PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
> > +	rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
> > +		PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
> > +
> > +	if (is_version(pcr, 0x524A, IC_VER_A)) {
> > +		rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
> > +			PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
> > +		rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
> > +			PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
> > +			PHY_SSCCR2_TIME2_WIDTH);
> > +		rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
> > +			PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
> > +			PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
> > +		rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
> > +			PHY_ANA1D_DEBUG_ADDR);
> > +		rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
> > +			PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
> > +			PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
> > +			PHY_DIG1E_RCLK_TX_EN_KEEP |
> > +			PHY_DIG1E_RCLK_TX_TERM_KEEP |
> > +			PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
> > +			PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
> > +			PHY_DIG1E_RX_EN_KEEP);
> > +	}
> > +
> > +	rtsx_pci_write_phy_register(pcr, PHY_ANA08,
> > +		PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
> > +		PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
> > +
> > +	return 0;
> > +}
> > +
> > +static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
> > +{
> > +	rts5249_extra_init_hw(pcr);
> > +
> > +	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
> > +		FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
> > +	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
> > +	rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
> > +		LDO_VCC_LMT_EN);
> > +	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
> > +	if (is_version(pcr, 0x524A, IC_VER_A)) {
> > +		rtsx_pci_write_register(pcr, LDO_DV18_CFG,
> > +			LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
> > +		rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
> > +			LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
> > +		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
> > +			LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
> > +		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
> > +			LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
> > +		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
> > +			LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
> > +		rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
> > +			SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct pcr_ops rts524a_pcr_ops = {
> > +	.write_phy = rts524a_write_phy,
> > +	.read_phy = rts524a_read_phy,
> > +	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
> > +	.extra_init_hw = rts524a_extra_init_hw,
> > +	.optimize_phy = rts524a_optimize_phy,
> > +	.turn_on_led = rtsx_base_turn_on_led,
> > +	.turn_off_led = rtsx_base_turn_off_led,
> > +	.enable_auto_blink = rtsx_base_enable_auto_blink,
> > +	.disable_auto_blink = rtsx_base_disable_auto_blink,
> > +	.card_power_on = rtsx_base_card_power_on,
> > +	.card_power_off = rtsx_base_card_power_off,
> > +	.switch_output_voltage = rtsx_base_switch_output_voltage,
> > +	.force_power_down = rtsx_base_force_power_down,
> > +};
> > +
> > +void rts524a_init_params(struct rtsx_pcr *pcr)
> > +{
> > +	rts5249_init_params(pcr);
> > +
> > +	pcr->ops = &rts524a_pcr_ops;
> > +}
> > +
> > diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c
> > index 81b9c2c..e6d97ad 100644
> > --- a/drivers/mfd/rtsx_pcr.c
> > +++ b/drivers/mfd/rtsx_pcr.c
> > @@ -58,6 +58,7 @@ static const struct pci_device_id rtsx_pci_ids[] = {
> >   	{ PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
> >   	{ PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
> >   	{ PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
> > +	{ PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
> >   	{ 0, }
> >   };
> >   
> > @@ -142,7 +143,7 @@ int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
> >   }
> >   EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
> >   
> > -int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
> > +int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
> >   {
> >   	int err, i, finished = 0;
> >   	u8 tmp;
> > @@ -174,9 +175,17 @@ int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
> >   
> >   	return 0;
> >   }
> > +
> > +int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
> > +{
> > +	if (pcr->ops->write_phy)
> > +		return pcr->ops->write_phy(pcr, addr, val);
> > +
> > +	return __rtsx_pci_write_phy_register(pcr, addr, val);
> > +}
> >   EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
> >   
> > -int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> > +int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> >   {
> >   	int err, i, finished = 0;
> >   	u16 data;
> > @@ -222,6 +231,14 @@ int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> >   
> >   	return 0;
> >   }
> > +
> > +int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> > +{
> > +	if (pcr->ops->read_phy)
> > +		return pcr->ops->read_phy(pcr, addr, val);
> > +
> > +	return __rtsx_pci_read_phy_register(pcr, addr, val);
> > +}
> >   EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
> >   
> >   void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
> > @@ -1093,6 +1110,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
> >   		rts5249_init_params(pcr);
> >   		break;
> >   
> > +	case 0x524A:
> > +		rts524a_init_params(pcr);
> > +		break;
> > +
> >   	case 0x5287:
> >   		rtl8411b_init_params(pcr);
> >   		break;
> > diff --git a/drivers/mfd/rtsx_pcr.h b/drivers/mfd/rtsx_pcr.h
> > index fe2bbb6..e7daf6f 100644
> > --- a/drivers/mfd/rtsx_pcr.h
> > +++ b/drivers/mfd/rtsx_pcr.h
> > @@ -27,12 +27,19 @@
> >   #define MIN_DIV_N_PCR		80
> >   #define MAX_DIV_N_PCR		208
> >   
> > +#define RTS524A_PME_FORCE_CTL		0xFF78
> > +#define RTS524A_PM_CTRL3		0xFF7E
> > +
> > +int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
> > +int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
> > +
> >   void rts5209_init_params(struct rtsx_pcr *pcr);
> >   void rts5229_init_params(struct rtsx_pcr *pcr);
> >   void rtl8411_init_params(struct rtsx_pcr *pcr);
> >   void rtl8402_init_params(struct rtsx_pcr *pcr);
> >   void rts5227_init_params(struct rtsx_pcr *pcr);
> >   void rts5249_init_params(struct rtsx_pcr *pcr);
> > +void rts524a_init_params(struct rtsx_pcr *pcr);
> >   void rtl8411b_init_params(struct rtsx_pcr *pcr);
> >   
> >   static inline u8 map_sd_drive(int idx)
> > diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
> > index 33cc63c..a392546 100644
> > --- a/include/linux/mfd/rtsx_pci.h
> > +++ b/include/linux/mfd/rtsx_pci.h
> > @@ -577,8 +577,16 @@
> >   
> >   #define CDRESUMECTL			0xFE52
> >   #define WAKE_SEL_CTL			0xFE54
> > +#define PCLK_CTL			0xFE55
> > +#define   PCLK_MODE_SEL			0x20
> >   #define PME_FORCE_CTL			0xFE56
> > +
> >   #define ASPM_FORCE_CTL			0xFE57
> > +#define   FORCE_ASPM_CTL0		0x10
> > +#define   FORCE_ASPM_VAL_MASK		0x03
> > +#define   FORCE_ASPM_L1_EN		0x02
> > +#define   FORCE_ASPM_L0_EN		0x01
> > +#define   FORCE_ASPM_NO_ASPM		0x00
> >   #define PM_CLK_FORCE_CTL		0xFE58
> >   #define FUNC_FORCE_CTL			0xFE59
> >   #define PERST_GLITCH_WIDTH		0xFE5C
> > @@ -590,7 +598,8 @@
> >   #define   HOST_ENTER_S3			2
> >   
> >   #define SDIO_CFG			0xFE70
> > -
> > +#define PM_EVENT_DEBUG			0xFE71
> > +#define   PME_DEBUG_0			0x08
> >   #define NFTS_TX_CTRL			0xFE72
> >   
> >   #define PWR_GATE_CTRL			0xFE75
> > @@ -602,12 +611,19 @@
> >   #define PWD_SUSPEND_EN			0xFE76
> >   #define LDO_PWR_SEL			0xFE78
> >   
> > +#define L1SUB_CONFIG1			0xFE8D
> > +#define L1SUB_CONFIG2			0xFE8E
> > +#define   L1SUB_AUTO_CFG		0x02
> > +#define L1SUB_CONFIG3			0xFE8F
> > +
> >   #define DUMMY_REG_RESET_0		0xFE90
> >   
> >   #define AUTOLOAD_CFG_BASE		0xFF00
> >   #define PETXCFG				0xFF03
> >   
> >   #define PM_CTRL1			0xFF44
> > +#define   CD_RESUME_EN_MASK		0xF0
> > +
> >   #define PM_CTRL2			0xFF45
> >   #define PM_CTRL3			0xFF46
> >   #define   SDIO_SEND_PME_EN		0x80
> > @@ -628,6 +644,61 @@
> >   #define IMAGE_FLAG_ADDR0		0xCE80
> >   #define IMAGE_FLAG_ADDR1		0xCE81
> >   
> > +#define RREF_CFG			0xFF6C
> > +#define   RREF_VBGSEL_MASK		0x38
> > +#define   RREF_VBGSEL_1V25		0x28
> > +
> > +#define OOBS_CONFIG			0xFF6E
> > +#define   OOBS_AUTOK_DIS		0x80
> > +#define   OOBS_VAL_MASK			0x1F
> > +
> > +#define LDO_DV18_CFG			0xFF70
> > +#define   LDO_DV18_SR_MASK		0xC0
> > +#define   LDO_DV18_SR_DF		0x40
> > +
> > +#define LDO_CONFIG2			0xFF71
> > +#define   LDO_D3318_MASK		0x07
> > +#define   LDO_D3318_33V			0x07
> > +#define   LDO_D3318_18V			0x02
> > +
> > +#define LDO_VCC_CFG0			0xFF72
> > +#define   LDO_VCC_LMTVTH_MASK		0x30
> > +#define   LDO_VCC_LMTVTH_2A		0x10
> > +
> > +#define LDO_VCC_CFG1			0xFF73
> > +#define   LDO_VCC_REF_TUNE_MASK		0x30
> > +#define   LDO_VCC_REF_1V2		0x20
> > +#define   LDO_VCC_TUNE_MASK		0x07
> > +#define   LDO_VCC_1V8			0x04
> > +#define   LDO_VCC_3V3			0x07
> > +#define   LDO_VCC_LMT_EN		0x08
> > +
> > +#define LDO_VIO_CFG			0xFF75
> > +#define   LDO_VIO_SR_MASK		0xC0
> > +#define   LDO_VIO_SR_DF			0x40
> > +#define   LDO_VIO_REF_TUNE_MASK		0x30
> > +#define   LDO_VIO_REF_1V2		0x20
> > +#define   LDO_VIO_TUNE_MASK		0x07
> > +#define   LDO_VIO_1V7			0x03
> > +#define   LDO_VIO_1V8			0x04
> > +#define   LDO_VIO_3V3			0x07
> > +
> > +#define LDO_DV12S_CFG			0xFF76
> > +#define   LDO_REF12_TUNE_MASK		0x18
> > +#define   LDO_REF12_TUNE_DF		0x10
> > +#define   LDO_D12_TUNE_MASK		0x07
> > +#define   LDO_D12_TUNE_DF		0x04
> > +
> > +#define LDO_AV12S_CFG			0xFF77
> > +#define   LDO_AV12S_TUNE_MASK		0x07
> > +#define   LDO_AV12S_TUNE_DF		0x04
> > +
> > +#define SD40_LDO_CTL1			0xFE7D
> > +#define   SD40_VIO_TUNE_MASK		0x70
> > +#define   SD40_VIO_TUNE_1V7		0x30
> > +#define   SD_VIO_LDO_1V8		0x40
> > +#define   SD_VIO_LDO_3V3		0x70
> > +
> >   /* Phy register */
> >   #define PHY_PCR				0x00
> >   #define   PHY_PCR_FORCE_CODE		0xB000
> > @@ -641,6 +712,10 @@
> >   #define PHY_RCR1			0x02
> >   #define   PHY_RCR1_ADP_TIME_4		0x0400
> >   #define   PHY_RCR1_VCO_COARSE		0x001F
> > +#define PHY_SSCCR2			0x02
> > +#define   PHY_SSCCR2_PLL_NCODE		0x0A00
> > +#define   PHY_SSCCR2_TIME0		0x001C
> > +#define   PHY_SSCCR2_TIME2_WIDTH	0x0003
> >   
> >   #define PHY_RCR2			0x03
> >   #define   PHY_RCR2_EMPHASE_EN		0x8000
> > @@ -649,6 +724,9 @@
> >   #define   PHY_RCR2_FREQSEL_12		0x0040
> >   #define   PHY_RCR2_CDR_SC_12P		0x0010
> >   #define   PHY_RCR2_CALIB_LATE		0x0002
> > +#define PHY_SSCCR3			0x03
> > +#define   PHY_SSCCR3_STEP_IN		0x2740
> > +#define   PHY_SSCCR3_CHECK_DELAY	0x0008
> >   
> >   #define PHY_RTCR			0x04
> >   #define PHY_RDR				0x05
> > @@ -663,6 +741,12 @@
> >   #define   PHY_TUNE_TUNED18		0x01C0
> >   #define   PHY_TUNE_TUNED12		0X0020
> >   #define   PHY_TUNE_TUNEA12		0x0004
> > +#define PHY_ANA08			0x08
> > +#define   PHY_ANA08_RX_EQ_DCGAIN	0x5000
> > +#define   PHY_ANA08_SEL_RX_EN		0x0400
> > +#define   PHY_ANA08_RX_EQ_VAL		0x03C0
> > +#define   PHY_ANA08_SCP			0x0020
> > +#define   PHY_ANA08_SEL_IPI		0x0004
> >   
> >   #define PHY_IMR				0x09
> >   #define PHY_BPCR			0x0A
> > @@ -698,12 +782,19 @@
> >   #define   PHY_REV_STOP_CLKWR		0x0004
> >   
> >   #define PHY_FLD0			0x1A
> > +#define PHY_ANA1A			0x1A
> > +#define   PHY_ANA1A_TXR_LOOPBACK	0x2000
> > +#define   PHY_ANA1A_RXT_BIST		0x0500
> > +#define   PHY_ANA1A_TXR_BIST		0x0040
> > +#define   PHY_ANA1A_REV			0x0006
> >   #define PHY_FLD1			0x1B
> >   #define PHY_FLD2			0x1C
> >   #define PHY_FLD3			0x1D
> >   #define   PHY_FLD3_TIMER_4		0x0800
> >   #define   PHY_FLD3_TIMER_6		0x0020
> >   #define   PHY_FLD3_RXDELINK		0x0004
> > +#define PHY_ANA1D			0x1D
> > +#define   PHY_ANA1D_DEBUG_ADDR		0x0004
> >   
> >   #define PHY_FLD4			0x1E
> >   #define   PHY_FLD4_FLDEN_SEL		0x4000
> > @@ -713,7 +804,18 @@
> >   #define   PHY_FLD4_BER_COUNT		0x00E0
> >   #define   PHY_FLD4_BER_TIMER		0x000A
> >   #define   PHY_FLD4_BER_CHK_EN		0x0001
> > -
> > +#define PHY_DIG1E			0x1E
> > +#define   PHY_DIG1E_REV			0x4000
> > +#define   PHY_DIG1E_D0_X_D1		0x1000
> > +#define   PHY_DIG1E_RX_ON_HOST		0x0800
> > +#define   PHY_DIG1E_RCLK_REF_HOST	0x0400
> > +#define   PHY_DIG1E_RCLK_TX_EN_KEEP	0x0040
> > +#define   PHY_DIG1E_RCLK_TX_TERM_KEEP	0x0020
> > +#define   PHY_DIG1E_RCLK_RX_EIDLE_ON	0x0010
> > +#define   PHY_DIG1E_TX_TERM_KEEP	0x0008
> > +#define   PHY_DIG1E_RX_TERM_KEEP	0x0004
> > +#define   PHY_DIG1E_TX_EN_KEEP		0x0002
> > +#define   PHY_DIG1E_RX_EN_KEEP		0x0001
> >   #define PHY_DUM_REG			0x1F
> >   
> >   #define PCR_SETTING_REG1		0x724
> > @@ -729,6 +831,8 @@ struct pcr_handle {
> >   };
> >   
> >   struct pcr_ops {
> > +	int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
> > +	int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
> >   	int		(*extra_init_hw)(struct rtsx_pcr *pcr);
> >   	int		(*optimize_phy)(struct rtsx_pcr *pcr);
> >   	int		(*turn_on_led)(struct rtsx_pcr *pcr);
> > @@ -830,6 +934,10 @@ struct rtsx_pcr {
> >   #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))
> >   #define PCI_VID(pcr)			((pcr)->pci->vendor)
> >   #define PCI_PID(pcr)			((pcr)->pci->device)
> > +#define is_version(pcr, pid, ver)				\
> > +	(CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
> > +#define pcr_dbg(pcr, fmt, arg...)				\
> > +	dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
> >   
> >   #define SDR104_PHASE(val)		((val) & 0xFF)
> >   #define SDR50_PHASE(val)		(((val) >> 8) & 0xFF)
> > @@ -899,4 +1007,17 @@ static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
> >   	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
> >   }
> >   
> > +static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
> > +	u16 mask, u16 append)
> > +{
> > +	int err;
> > +	u16 val;
> > +
> > +	err = rtsx_pci_read_phy_register(pcr, addr, &val);
> > +	if (err < 0)
> > +		return err;
> > +
> > +	return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
> > +}
> > +
> >   #endif

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [RESEND PATCH v2 5/9] mfd: rtsx: update phy register
  2015-01-22  7:30 ` [RESEND PATCH v2 5/9] mfd: rtsx: update phy register micky_ching
@ 2015-02-16 14:07   ` Lee Jones
  0 siblings, 0 replies; 19+ messages in thread
From: Lee Jones @ 2015-02-16 14:07 UTC (permalink / raw)
  To: micky_ching; +Cc: sameo, devel, linux-kernel, gregkh, rogerable, wei_wang

On Thu, 22 Jan 2015, micky_ching@realsil.com.cn wrote:

> From: Micky Ching <micky_ching@realsil.com.cn>
> 
> update phy register value and using direct value instead of macros.
> It is much easier to debug using constant value than a lot of macros.
> We usually need compare the value directly to check the configure.

This is no longer an adequate description of the patch.

> Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
> ---
>  drivers/mfd/rts5249.c        |  55 ++++++++++++----------
>  include/linux/mfd/rtsx_pci.h | 109 ++++++++++++++++++++++---------------------
>  2 files changed, 85 insertions(+), 79 deletions(-)
> 
> diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
> index 2fe2854..d8072f6 100644
> --- a/drivers/mfd/rts5249.c
> +++ b/drivers/mfd/rts5249.c
> @@ -132,57 +132,62 @@ static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
>  	if (err < 0)
>  		return err;
>  
> -	err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV,
> -			PHY_REG_REV_RESV | PHY_REG_REV_RXIDLE_LATCHED |
> -			PHY_REG_REV_P1_EN | PHY_REG_REV_RXIDLE_EN |
> -			PHY_REG_REV_RX_PWST | PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 |
> -			PHY_REG_REV_STOP_CLKRD | PHY_REG_REV_STOP_CLKWR);
> +	err = rtsx_pci_write_phy_register(pcr, PHY_REV,
> +		PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED |
> +		PHY_REV_P1_EN | PHY_REV_RXIDLE_EN |
> +		PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST |
> +		PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD |
> +		PHY_REV_STOP_CLKWR);

The tabbing changes make it difficult to see what you're _really_
doing.  If you think the tabs are important (I think they were better
before personally), then send them as a separate patch.

>  	if (err < 0)
>  		return err;
>  
>  	msleep(1);
>  
>  	err = rtsx_pci_write_phy_register(pcr, PHY_BPCR,
> -			PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
> -			PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);
> +		PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL |
> +		PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN);

More nonsense?

>  	if (err < 0)
>  		return err;
> +
>  	err = rtsx_pci_write_phy_register(pcr, PHY_PCR,
> -			PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
> -			PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
> -			PHY_PCR_RSSI_EN);
> +		PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
> +		PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 |
> +		PHY_PCR_RSSI_EN | PHY_PCR_RX10K);

Etc.

I'm going to stop here.  Please resubmit this patch properly.

[...]

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A
  2015-01-22  7:30 ` [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A micky_ching
  2015-02-02  1:07   ` 敬锐
@ 2015-02-16 14:28   ` Lee Jones
  2015-02-25  3:27     ` 敬锐
  1 sibling, 1 reply; 19+ messages in thread
From: Lee Jones @ 2015-02-16 14:28 UTC (permalink / raw)
  To: micky_ching; +Cc: sameo, devel, linux-kernel, gregkh, rogerable, wei_wang

On Thu, 22 Jan 2015, micky_ching@realsil.com.cn wrote:

> From: Micky Ching <micky_ching@realsil.com.cn>
> 
> add support for new chip rts524A.
> 
> Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
> ---
>  drivers/mfd/rts5249.c        | 186 ++++++++++++++++++++++++++++++++++++-------
>  drivers/mfd/rtsx_pcr.c       |  25 +++++-
>  drivers/mfd/rtsx_pcr.h       |   7 ++
>  include/linux/mfd/rtsx_pci.h | 125 ++++++++++++++++++++++++++++-
>  4 files changed, 310 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
> index 3977946..97dde92 100644
> --- a/drivers/mfd/rts5249.c
> +++ b/drivers/mfd/rts5249.c
> @@ -65,15 +65,17 @@ static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
>  			0xFF, driving[drive_sel][2]);
>  }
>  
> -static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
> +static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
>  {
>  	u32 reg;
>  
>  	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
>  	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
>  
> -	if (!rtsx_vendor_setting_valid(reg))
> +	if (!rtsx_vendor_setting_valid(reg)) {
> +		pcr_dbg(pcr, "skip fetch vendor setting\n");
>  		return;
> +	}
>  
>  	pcr->aspm_en = rtsx_reg_to_aspm(reg);
>  	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
> @@ -87,15 +89,21 @@ static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
>  		pcr->flags |= PCR_REVERSE_SOCKET;
>  }
>  
> -static void rts5249_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
> +static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
>  {
>  	/* Set relink_time to 0 */
>  	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
>  	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
>  	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
>  
> -	if (pm_state == HOST_ENTER_S3)
> -		rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
> +	if (pm_state == HOST_ENTER_S3) {
> +		if (PCI_PID(pcr) == 0x524A)

Please define these magic numbers.

> +			rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
> +				D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
> +		else if (PCI_PID(pcr) == 0x5249)
> +			rtsx_pci_write_register(pcr, PM_CTRL3,
> +				D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
> +	}

> +		if (PCI_PID(pcr) == 0x524A)

Please define these magic numbers.

This chunk might be better written as:

        if (pm_state == HOST_ENTER_S3) {
                ctrlreg = (PCI_PID(pcr) == 0x524A) ?
                        RTS524A_PM_CTRL3 : PM_CTRL3;

                rtsx_pci_write_register(pcr, ctrlreg,
                        D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
        }

>  	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
>  }
> @@ -104,6 +112,8 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
>  {
>  	rtsx_pci_init_cmd(pcr);
>  
> +	/* Rest L1SUB Config */
> +	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
>  	/* Configure GPIO as output */
>  	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
>  	/* Reset ASPM state to default value */
> @@ -189,27 +199,27 @@ static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
>  		PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12);
>  }
>  
> -static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
> +static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr)
>  {
>  	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
>  }
>  
> -static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
> +static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr)
>  {
>  	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
>  }
>  
> -static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
> +static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
>  {
>  	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
>  }
>  
> -static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
> +static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
>  {
>  	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
>  }
>  
> -static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
> +static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card)
>  {
>  	int err;
>  
> @@ -236,7 +246,7 @@ static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
>  	return 0;
>  }
>  
> -static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
> +static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card)
>  {
>  	rtsx_pci_init_cmd(pcr);
>  	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
> @@ -246,22 +256,31 @@ static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
>  	return rtsx_pci_send_cmd(pcr, 100);
>  }
>  
> -static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
> +static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
>  {
>  	int err;
> +	u16 append;
>  
> -	if (voltage == OUTPUT_3V3) {
> -		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
> -		if (err < 0)
> -			return err;
> -	} else if (voltage == OUTPUT_1V8) {
> -		err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
> +	switch (voltage) {
> +	case OUTPUT_3V3:
> +		err = rtsx_pci_update_phy(pcr, PHY_TUNE, 0xFC3F, 0x03C0);

Define these magic numbers please.

>  		if (err < 0)
>  			return err;
> -		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
> +		break;
> +	case OUTPUT_1V8:
> +		append = 0x0100;

What is append?

> +		if (PCI_PID(pcr) == 0x5249) {
> +			err = rtsx_pci_update_phy(pcr, PHY_BACR, 0xFFF3, 0);
> +			if (err < 0)
> +				return err;
> +			append = 0x0080;
> +		}
> +
> +		err = rtsx_pci_update_phy(pcr, PHY_TUNE, 0xFC3F, append);
>  		if (err < 0)
>  			return err;
> -	} else {
> +		break;
> +	default:

You might want to provide your user with a reason for bailing out.

>  		return -EINVAL;
>  	}
>  
> @@ -272,17 +291,17 @@ static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
>  }
>  
>  static const struct pcr_ops rts5249_pcr_ops = {
> -	.fetch_vendor_settings = rts5249_fetch_vendor_settings,
> +	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
>  	.extra_init_hw = rts5249_extra_init_hw,
>  	.optimize_phy = rts5249_optimize_phy,
> -	.turn_on_led = rts5249_turn_on_led,
> -	.turn_off_led = rts5249_turn_off_led,
> -	.enable_auto_blink = rts5249_enable_auto_blink,
> -	.disable_auto_blink = rts5249_disable_auto_blink,
> -	.card_power_on = rts5249_card_power_on,
> -	.card_power_off = rts5249_card_power_off,
> -	.switch_output_voltage = rts5249_switch_output_voltage,
> -	.force_power_down = rts5249_force_power_down,
> +	.turn_on_led = rtsx_base_turn_on_led,
> +	.turn_off_led = rtsx_base_turn_off_led,
> +	.enable_auto_blink = rtsx_base_enable_auto_blink,
> +	.disable_auto_blink = rtsx_base_disable_auto_blink,
> +	.card_power_on = rtsx_base_card_power_on,
> +	.card_power_off = rtsx_base_card_power_off,
> +	.switch_output_voltage = rtsx_base_switch_output_voltage,
> +	.force_power_down = rtsx_base_force_power_down,
>  };
>  
>  /* SD Pull Control Enable:
> @@ -357,3 +376,112 @@ void rts5249_init_params(struct rtsx_pcr *pcr)
>  	pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
>  	pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
>  }
> +
> +static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
> +{
> +	addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
> +
> +	return __rtsx_pci_write_phy_register(pcr, addr, val);
> +}
> +
> +static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> +{
> +	addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr;
> +
> +	return __rtsx_pci_read_phy_register(pcr, addr, val);
> +}
> +
> +static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
> +{
> +	int err;
> +
> +	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
> +		D3_DELINK_MODE_EN, 0x00);
> +	if (err < 0)
> +		return err;
> +
> +	rtsx_pci_write_phy_register(pcr, PHY_PCR,
> +		PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
> +		PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
> +	rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
> +		PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
> +
> +	if (is_version(pcr, 0x524A, IC_VER_A)) {
> +		rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
> +			PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
> +		rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
> +			PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
> +			PHY_SSCCR2_TIME2_WIDTH);
> +		rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
> +			PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
> +			PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
> +		rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
> +			PHY_ANA1D_DEBUG_ADDR);
> +		rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
> +			PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
> +			PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
> +			PHY_DIG1E_RCLK_TX_EN_KEEP |
> +			PHY_DIG1E_RCLK_TX_TERM_KEEP |
> +			PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
> +			PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
> +			PHY_DIG1E_RX_EN_KEEP);
> +	}
> +
> +	rtsx_pci_write_phy_register(pcr, PHY_ANA08,
> +		PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
> +		PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);

To the uninitiated this function is mostly randomness.  How about some
nice comments to illuminate?

> +	return 0;
> +}
> +
> +static int rts524a_extra_init_hw(struct rtsx_pcr *pcr)
> +{
> +	rts5249_extra_init_hw(pcr);
> +
> +	rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
> +		FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN);
> +	rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
> +	rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN,
> +		LDO_VCC_LMT_EN);
> +	rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
> +	if (is_version(pcr, 0x524A, IC_VER_A)) {
> +		rtsx_pci_write_register(pcr, LDO_DV18_CFG,
> +			LDO_DV18_SR_MASK, LDO_DV18_SR_DF);
> +		rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
> +			LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2);
> +		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
> +			LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2);
> +		rtsx_pci_write_register(pcr, LDO_VIO_CFG,
> +			LDO_VIO_SR_MASK, LDO_VIO_SR_DF);
> +		rtsx_pci_write_register(pcr, LDO_DV12S_CFG,
> +			LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF);
> +		rtsx_pci_write_register(pcr, SD40_LDO_CTL1,
> +			SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7);
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct pcr_ops rts524a_pcr_ops = {
> +	.write_phy = rts524a_write_phy,
> +	.read_phy = rts524a_read_phy,
> +	.fetch_vendor_settings = rtsx_base_fetch_vendor_settings,
> +	.extra_init_hw = rts524a_extra_init_hw,
> +	.optimize_phy = rts524a_optimize_phy,
> +	.turn_on_led = rtsx_base_turn_on_led,
> +	.turn_off_led = rtsx_base_turn_off_led,
> +	.enable_auto_blink = rtsx_base_enable_auto_blink,
> +	.disable_auto_blink = rtsx_base_disable_auto_blink,
> +	.card_power_on = rtsx_base_card_power_on,
> +	.card_power_off = rtsx_base_card_power_off,
> +	.switch_output_voltage = rtsx_base_switch_output_voltage,
> +	.force_power_down = rtsx_base_force_power_down,
> +};
> +
> +void rts524a_init_params(struct rtsx_pcr *pcr)
> +{
> +	rts5249_init_params(pcr);
> +
> +	pcr->ops = &rts524a_pcr_ops;
> +}
> +
> diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c
> index 81b9c2c..e6d97ad 100644
> --- a/drivers/mfd/rtsx_pcr.c
> +++ b/drivers/mfd/rtsx_pcr.c
> @@ -58,6 +58,7 @@ static const struct pci_device_id rtsx_pci_ids[] = {
>  	{ PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
>  	{ PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
>  	{ PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
> +	{ PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
>  	{ 0, }
>  };
>  
> @@ -142,7 +143,7 @@ int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
>  }
>  EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
>  
> -int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
> +int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
>  {
>  	int err, i, finished = 0;
>  	u8 tmp;
> @@ -174,9 +175,17 @@ int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
>  
>  	return 0;
>  }
> +
> +int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
> +{
> +	if (pcr->ops->write_phy)
> +		return pcr->ops->write_phy(pcr, addr, val);
> +
> +	return __rtsx_pci_write_phy_register(pcr, addr, val);
> +}
>  EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
>  
> -int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> +int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
>  {
>  	int err, i, finished = 0;
>  	u16 data;
> @@ -222,6 +231,14 @@ int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
>  
>  	return 0;
>  }
> +
> +int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
> +{
> +	if (pcr->ops->read_phy)
> +		return pcr->ops->read_phy(pcr, addr, val);
> +
> +	return __rtsx_pci_read_phy_register(pcr, addr, val);
> +}
>  EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
>  
>  void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
> @@ -1093,6 +1110,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
>  		rts5249_init_params(pcr);
>  		break;
>  
> +	case 0x524A:
> +		rts524a_init_params(pcr);
> +		break;
> +
>  	case 0x5287:
>  		rtl8411b_init_params(pcr);
>  		break;
> diff --git a/drivers/mfd/rtsx_pcr.h b/drivers/mfd/rtsx_pcr.h
> index fe2bbb6..e7daf6f 100644
> --- a/drivers/mfd/rtsx_pcr.h
> +++ b/drivers/mfd/rtsx_pcr.h
> @@ -27,12 +27,19 @@
>  #define MIN_DIV_N_PCR		80
>  #define MAX_DIV_N_PCR		208
>  
> +#define RTS524A_PME_FORCE_CTL		0xFF78
> +#define RTS524A_PM_CTRL3		0xFF7E
> +
> +int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
> +int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
> +
>  void rts5209_init_params(struct rtsx_pcr *pcr);
>  void rts5229_init_params(struct rtsx_pcr *pcr);
>  void rtl8411_init_params(struct rtsx_pcr *pcr);
>  void rtl8402_init_params(struct rtsx_pcr *pcr);
>  void rts5227_init_params(struct rtsx_pcr *pcr);
>  void rts5249_init_params(struct rtsx_pcr *pcr);
> +void rts524a_init_params(struct rtsx_pcr *pcr);
>  void rtl8411b_init_params(struct rtsx_pcr *pcr);
>  
>  static inline u8 map_sd_drive(int idx)
> diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
> index 33cc63c..a392546 100644
> --- a/include/linux/mfd/rtsx_pci.h
> +++ b/include/linux/mfd/rtsx_pci.h
> @@ -577,8 +577,16 @@
>  
>  #define CDRESUMECTL			0xFE52
>  #define WAKE_SEL_CTL			0xFE54
> +#define PCLK_CTL			0xFE55
> +#define   PCLK_MODE_SEL			0x20
>  #define PME_FORCE_CTL			0xFE56
> +
>  #define ASPM_FORCE_CTL			0xFE57
> +#define   FORCE_ASPM_CTL0		0x10
> +#define   FORCE_ASPM_VAL_MASK		0x03
> +#define   FORCE_ASPM_L1_EN		0x02
> +#define   FORCE_ASPM_L0_EN		0x01
> +#define   FORCE_ASPM_NO_ASPM		0x00
>  #define PM_CLK_FORCE_CTL		0xFE58
>  #define FUNC_FORCE_CTL			0xFE59
>  #define PERST_GLITCH_WIDTH		0xFE5C
> @@ -590,7 +598,8 @@
>  #define   HOST_ENTER_S3			2
>  
>  #define SDIO_CFG			0xFE70
> -
> +#define PM_EVENT_DEBUG			0xFE71
> +#define   PME_DEBUG_0			0x08
>  #define NFTS_TX_CTRL			0xFE72
>  
>  #define PWR_GATE_CTRL			0xFE75
> @@ -602,12 +611,19 @@
>  #define PWD_SUSPEND_EN			0xFE76
>  #define LDO_PWR_SEL			0xFE78
>  
> +#define L1SUB_CONFIG1			0xFE8D
> +#define L1SUB_CONFIG2			0xFE8E
> +#define   L1SUB_AUTO_CFG		0x02
> +#define L1SUB_CONFIG3			0xFE8F
> +
>  #define DUMMY_REG_RESET_0		0xFE90
>  
>  #define AUTOLOAD_CFG_BASE		0xFF00
>  #define PETXCFG				0xFF03
>  
>  #define PM_CTRL1			0xFF44
> +#define   CD_RESUME_EN_MASK		0xF0
> +
>  #define PM_CTRL2			0xFF45
>  #define PM_CTRL3			0xFF46
>  #define   SDIO_SEND_PME_EN		0x80
> @@ -628,6 +644,61 @@
>  #define IMAGE_FLAG_ADDR0		0xCE80
>  #define IMAGE_FLAG_ADDR1		0xCE81
>  
> +#define RREF_CFG			0xFF6C
> +#define   RREF_VBGSEL_MASK		0x38
> +#define   RREF_VBGSEL_1V25		0x28
> +
> +#define OOBS_CONFIG			0xFF6E
> +#define   OOBS_AUTOK_DIS		0x80
> +#define   OOBS_VAL_MASK			0x1F
> +
> +#define LDO_DV18_CFG			0xFF70
> +#define   LDO_DV18_SR_MASK		0xC0
> +#define   LDO_DV18_SR_DF		0x40
> +
> +#define LDO_CONFIG2			0xFF71
> +#define   LDO_D3318_MASK		0x07
> +#define   LDO_D3318_33V			0x07
> +#define   LDO_D3318_18V			0x02
> +
> +#define LDO_VCC_CFG0			0xFF72
> +#define   LDO_VCC_LMTVTH_MASK		0x30
> +#define   LDO_VCC_LMTVTH_2A		0x10
> +
> +#define LDO_VCC_CFG1			0xFF73
> +#define   LDO_VCC_REF_TUNE_MASK		0x30
> +#define   LDO_VCC_REF_1V2		0x20
> +#define   LDO_VCC_TUNE_MASK		0x07
> +#define   LDO_VCC_1V8			0x04
> +#define   LDO_VCC_3V3			0x07
> +#define   LDO_VCC_LMT_EN		0x08
> +
> +#define LDO_VIO_CFG			0xFF75
> +#define   LDO_VIO_SR_MASK		0xC0
> +#define   LDO_VIO_SR_DF			0x40
> +#define   LDO_VIO_REF_TUNE_MASK		0x30
> +#define   LDO_VIO_REF_1V2		0x20
> +#define   LDO_VIO_TUNE_MASK		0x07
> +#define   LDO_VIO_1V7			0x03
> +#define   LDO_VIO_1V8			0x04
> +#define   LDO_VIO_3V3			0x07
> +
> +#define LDO_DV12S_CFG			0xFF76
> +#define   LDO_REF12_TUNE_MASK		0x18
> +#define   LDO_REF12_TUNE_DF		0x10
> +#define   LDO_D12_TUNE_MASK		0x07
> +#define   LDO_D12_TUNE_DF		0x04
> +
> +#define LDO_AV12S_CFG			0xFF77
> +#define   LDO_AV12S_TUNE_MASK		0x07
> +#define   LDO_AV12S_TUNE_DF		0x04
> +
> +#define SD40_LDO_CTL1			0xFE7D
> +#define   SD40_VIO_TUNE_MASK		0x70
> +#define   SD40_VIO_TUNE_1V7		0x30
> +#define   SD_VIO_LDO_1V8		0x40
> +#define   SD_VIO_LDO_3V3		0x70
> +
>  /* Phy register */
>  #define PHY_PCR				0x00
>  #define   PHY_PCR_FORCE_CODE		0xB000
> @@ -641,6 +712,10 @@
>  #define PHY_RCR1			0x02
>  #define   PHY_RCR1_ADP_TIME_4		0x0400
>  #define   PHY_RCR1_VCO_COARSE		0x001F
> +#define PHY_SSCCR2			0x02
> +#define   PHY_SSCCR2_PLL_NCODE		0x0A00
> +#define   PHY_SSCCR2_TIME0		0x001C
> +#define   PHY_SSCCR2_TIME2_WIDTH	0x0003
>  
>  #define PHY_RCR2			0x03
>  #define   PHY_RCR2_EMPHASE_EN		0x8000
> @@ -649,6 +724,9 @@
>  #define   PHY_RCR2_FREQSEL_12		0x0040
>  #define   PHY_RCR2_CDR_SC_12P		0x0010
>  #define   PHY_RCR2_CALIB_LATE		0x0002
> +#define PHY_SSCCR3			0x03
> +#define   PHY_SSCCR3_STEP_IN		0x2740
> +#define   PHY_SSCCR3_CHECK_DELAY	0x0008
>  
>  #define PHY_RTCR			0x04
>  #define PHY_RDR				0x05
> @@ -663,6 +741,12 @@
>  #define   PHY_TUNE_TUNED18		0x01C0
>  #define   PHY_TUNE_TUNED12		0X0020
>  #define   PHY_TUNE_TUNEA12		0x0004
> +#define PHY_ANA08			0x08
> +#define   PHY_ANA08_RX_EQ_DCGAIN	0x5000
> +#define   PHY_ANA08_SEL_RX_EN		0x0400
> +#define   PHY_ANA08_RX_EQ_VAL		0x03C0
> +#define   PHY_ANA08_SCP			0x0020
> +#define   PHY_ANA08_SEL_IPI		0x0004
>  
>  #define PHY_IMR				0x09
>  #define PHY_BPCR			0x0A
> @@ -698,12 +782,19 @@
>  #define   PHY_REV_STOP_CLKWR		0x0004
>  
>  #define PHY_FLD0			0x1A
> +#define PHY_ANA1A			0x1A
> +#define   PHY_ANA1A_TXR_LOOPBACK	0x2000
> +#define   PHY_ANA1A_RXT_BIST		0x0500
> +#define   PHY_ANA1A_TXR_BIST		0x0040
> +#define   PHY_ANA1A_REV			0x0006
>  #define PHY_FLD1			0x1B
>  #define PHY_FLD2			0x1C
>  #define PHY_FLD3			0x1D
>  #define   PHY_FLD3_TIMER_4		0x0800
>  #define   PHY_FLD3_TIMER_6		0x0020
>  #define   PHY_FLD3_RXDELINK		0x0004
> +#define PHY_ANA1D			0x1D
> +#define   PHY_ANA1D_DEBUG_ADDR		0x0004
>  
>  #define PHY_FLD4			0x1E
>  #define   PHY_FLD4_FLDEN_SEL		0x4000
> @@ -713,7 +804,18 @@
>  #define   PHY_FLD4_BER_COUNT		0x00E0
>  #define   PHY_FLD4_BER_TIMER		0x000A
>  #define   PHY_FLD4_BER_CHK_EN		0x0001
> -
> +#define PHY_DIG1E			0x1E
> +#define   PHY_DIG1E_REV			0x4000
> +#define   PHY_DIG1E_D0_X_D1		0x1000
> +#define   PHY_DIG1E_RX_ON_HOST		0x0800
> +#define   PHY_DIG1E_RCLK_REF_HOST	0x0400
> +#define   PHY_DIG1E_RCLK_TX_EN_KEEP	0x0040
> +#define   PHY_DIG1E_RCLK_TX_TERM_KEEP	0x0020
> +#define   PHY_DIG1E_RCLK_RX_EIDLE_ON	0x0010
> +#define   PHY_DIG1E_TX_TERM_KEEP	0x0008
> +#define   PHY_DIG1E_RX_TERM_KEEP	0x0004
> +#define   PHY_DIG1E_TX_EN_KEEP		0x0002
> +#define   PHY_DIG1E_RX_EN_KEEP		0x0001
>  #define PHY_DUM_REG			0x1F
>  
>  #define PCR_SETTING_REG1		0x724
> @@ -729,6 +831,8 @@ struct pcr_handle {
>  };
>  
>  struct pcr_ops {
> +	int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
> +	int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
>  	int		(*extra_init_hw)(struct rtsx_pcr *pcr);
>  	int		(*optimize_phy)(struct rtsx_pcr *pcr);
>  	int		(*turn_on_led)(struct rtsx_pcr *pcr);
> @@ -830,6 +934,10 @@ struct rtsx_pcr {
>  #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))
>  #define PCI_VID(pcr)			((pcr)->pci->vendor)
>  #define PCI_PID(pcr)			((pcr)->pci->device)
> +#define is_version(pcr, pid, ver)				\
> +	(CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
> +#define pcr_dbg(pcr, fmt, arg...)				\
> +	dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
>  
>  #define SDR104_PHASE(val)		((val) & 0xFF)
>  #define SDR50_PHASE(val)		(((val) >> 8) & 0xFF)
> @@ -899,4 +1007,17 @@ static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
>  	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
>  }
>  
> +static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
> +	u16 mask, u16 append)
> +{
> +	int err;
> +	u16 val;
> +
> +	err = rtsx_pci_read_phy_register(pcr, addr, &val);
> +	if (err < 0)
> +		return err;
> +
> +	return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
> +}

Why is this in here?

>  #endif

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [RESEND PATCH v2 6/9] mfd: rtsx: remove LCTLR defination
  2015-01-22  7:30 ` [RESEND PATCH v2 6/9] mfd: rtsx: remove LCTLR defination micky_ching
@ 2015-02-16 14:31   ` Lee Jones
  0 siblings, 0 replies; 19+ messages in thread
From: Lee Jones @ 2015-02-16 14:31 UTC (permalink / raw)
  To: micky_ching; +Cc: sameo, devel, linux-kernel, gregkh, rogerable, wei_wang

On Thu, 22 Jan 2015, micky_ching@realsil.com.cn wrote:

> From: Micky Ching <micky_ching@realsil.com.cn>
> 
> To enable/disable ASPM we should find LINK CONTROL register
> in PCI config space. All old chip use 0x80 address, but new
> chip may use another address, so we using pci_find_capability()
> to get LINK CONTROL address.
> 
> rtsx_gops.c was removed, we consider to put some common operations
> to this file, but the actual thing is, only a group of chips
> are in common ops1, and another group of chips in common ops2,
> it is hard to decide put which ops into generic ops file.
> 
> Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
> ---
>  drivers/mfd/Makefile         |  2 +-
>  drivers/mfd/rts5227.c        |  2 +-
>  drivers/mfd/rts5249.c        |  3 +--
>  drivers/mfd/rtsx_gops.c      | 37 -------------------------------------
>  drivers/mfd/rtsx_pcr.c       | 22 +++++++++++++++++-----
>  include/linux/mfd/rtsx_pci.h | 10 +---------
>  6 files changed, 21 insertions(+), 55 deletions(-)
>  delete mode 100644 drivers/mfd/rtsx_gops.c

Acked-by: Lee Jones <lee.jones@linaro.org>

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [RESEND PATCH v2 8/9] mfd: rtsx: add support for rts525A
  2015-01-22  7:30 ` [RESEND PATCH v2 8/9] mfd: rtsx: add support for rts525A micky_ching
@ 2015-02-16 14:37   ` Lee Jones
  0 siblings, 0 replies; 19+ messages in thread
From: Lee Jones @ 2015-02-16 14:37 UTC (permalink / raw)
  To: micky_ching; +Cc: sameo, devel, linux-kernel, gregkh, rogerable, wei_wang

On Thu, 22 Jan 2015, micky_ching@realsil.com.cn wrote:

> From: Micky Ching <micky_ching@realsil.com.cn>
> 
> add support for new chip rts525A.
> 
> Signed-off-by: Micky Ching <micky_ching@realsil.com.cn>
> ---
>  drivers/mfd/rts5249.c        | 104 ++++++++++++++++++++++++++++++++++++++++++-
>  drivers/mfd/rtsx_pcr.c       |  13 ++++--
>  drivers/mfd/rtsx_pcr.h       |   1 +
>  include/linux/mfd/rtsx_pci.h |  15 +++++++
>  4 files changed, 129 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mfd/rts5249.c b/drivers/mfd/rts5249.c
> index 97dde92..134e03f 100644
> --- a/drivers/mfd/rts5249.c
> +++ b/drivers/mfd/rts5249.c
> @@ -97,7 +97,7 @@ static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
>  	rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
>  
>  	if (pm_state == HOST_ENTER_S3) {
> -		if (PCI_PID(pcr) == 0x524A)
> +		if (PCI_PID(pcr) == 0x524A || PCI_PID(pcr) == 0x525A)

Please consider holding a pm_ctrl_reg attribute in the device data
structure, then only doing this once during initialisation.

Other than that, I have the same comments as before.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A
  2015-02-16 14:28   ` Lee Jones
@ 2015-02-25  3:27     ` 敬锐
  2015-02-25  7:21       ` Lee Jones
  0 siblings, 1 reply; 19+ messages in thread
From: 敬锐 @ 2015-02-25  3:27 UTC (permalink / raw)
  To: Lee Jones; +Cc: sameo, devel, linux-kernel, gregkh, rogerable, 王炜

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 4826 bytes --]


On 02/16/2015 10:28 PM, Lee Jones wrote:
>
> +static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
> +{
> +	int err;
> +
> +	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
> +		D3_DELINK_MODE_EN, 0x00);
> +	if (err < 0)
> +		return err;
> +
> +	rtsx_pci_write_phy_register(pcr, PHY_PCR,
> +		PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
> +		PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
> +	rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
> +		PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
> +
> +	if (is_version(pcr, 0x524A, IC_VER_A)) {
> +		rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
> +			PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
> +		rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
> +			PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
> +			PHY_SSCCR2_TIME2_WIDTH);
> +		rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
> +			PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
> +			PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
> +		rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
> +			PHY_ANA1D_DEBUG_ADDR);
> +		rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
> +			PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
> +			PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
> +			PHY_DIG1E_RCLK_TX_EN_KEEP |
> +			PHY_DIG1E_RCLK_TX_TERM_KEEP |
> +			PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
> +			PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
> +			PHY_DIG1E_RX_EN_KEEP);
> +	}
> +
> +	rtsx_pci_write_phy_register(pcr, PHY_ANA08,
> +		PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
> +		PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
> To the uninitiated this function is mostly randomness.  How about some
> nice comments to illuminate?
I'm not clear with these setting either, it is used to fix some phy 
setting, the default phy setting
it not stable on some special platform, so we have to modify them by driver,
newer version of chip will change its default value to more stable 
configure, so some value is
no need to setting for Version B/C...

>
>> diff --git a/drivers/mfd/rtsx_pcr.h b/drivers/mfd/rtsx_pcr.h
>> index fe2bbb6..e7daf6f 100644
>> --- a/drivers/mfd/rtsx_pcr.h
>> +++ b/drivers/mfd/rtsx_pcr.h
>> @@ -27,12 +27,19 @@
>>   #define MIN_DIV_N_PCR		80
>>   #define MAX_DIV_N_PCR		208
>>   
>> +#define RTS524A_PME_FORCE_CTL		0xFF78
>> +#define RTS524A_PM_CTRL3		0xFF7E
>> +
>> +int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
>> +int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
>> +
>>   void rts5209_init_params(struct rtsx_pcr *pcr);
>>   void rts5229_init_params(struct rtsx_pcr *pcr);
>>   void rtl8411_init_params(struct rtsx_pcr *pcr);
>>   void rtl8402_init_params(struct rtsx_pcr *pcr);
>>   void rts5227_init_params(struct rtsx_pcr *pcr);
>>   void rts5249_init_params(struct rtsx_pcr *pcr);
>> +void rts524a_init_params(struct rtsx_pcr *pcr);
>>   void rtl8411b_init_params(struct rtsx_pcr *pcr);
>>   
>>   static inline u8 map_sd_drive(int idx)
>> diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
>> index 33cc63c..a392546 100644
>> --- a/include/linux/mfd/rtsx_pci.h
>> +++ b/include/linux/mfd/rtsx_pci.h
>> @@ -577,8 +577,16 @@
>>
>>   
>>   #define PCR_SETTING_REG1		0x724
>> @@ -729,6 +831,8 @@ struct pcr_handle {
>>   };
>>   
>>   struct pcr_ops {
>> +	int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
>> +	int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
>>   	int		(*extra_init_hw)(struct rtsx_pcr *pcr);
>>   	int		(*optimize_phy)(struct rtsx_pcr *pcr);
>>   	int		(*turn_on_led)(struct rtsx_pcr *pcr);
>> @@ -830,6 +934,10 @@ struct rtsx_pcr {
>>   #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))
>>   #define PCI_VID(pcr)			((pcr)->pci->vendor)
>>   #define PCI_PID(pcr)			((pcr)->pci->device)
>> +#define is_version(pcr, pid, ver)				\
>> +	(CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
>> +#define pcr_dbg(pcr, fmt, arg...)				\
>> +	dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
>>   
>>   #define SDR104_PHASE(val)		((val) & 0xFF)
>>   #define SDR50_PHASE(val)		(((val) >> 8) & 0xFF)
>> @@ -899,4 +1007,17 @@ static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
>>   	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
>>   }
>>   
>> +static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
>> +	u16 mask, u16 append)
>> +{
>> +	int err;
>> +	u16 val;
>> +
>> +	err = rtsx_pci_read_phy_register(pcr, addr, &val);
>> +	if (err < 0)
>> +		return err;
>> +
>> +	return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
>> +}
> Why is this in here?
This is a good api for update phy register, mmc/ms driver can use this 
function.
>
>>   #endif
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^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A
  2015-02-25  3:27     ` 敬锐
@ 2015-02-25  7:21       ` Lee Jones
  0 siblings, 0 replies; 19+ messages in thread
From: Lee Jones @ 2015-02-25  7:21 UTC (permalink / raw)
  To: 敬锐
  Cc: sameo, devel, linux-kernel, gregkh, rogerable, 王炜

On Wed, 25 Feb 2015, 敬锐 wrote:

> 
> On 02/16/2015 10:28 PM, Lee Jones wrote:
> >
> > +static int rts524a_optimize_phy(struct rtsx_pcr *pcr)
> > +{
> > +	int err;
> > +
> > +	err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3,
> > +		D3_DELINK_MODE_EN, 0x00);
> > +	if (err < 0)
> > +		return err;
> > +
> > +	rtsx_pci_write_phy_register(pcr, PHY_PCR,
> > +		PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 |
> > +		PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN);
> > +	rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
> > +		PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
> > +
> > +	if (is_version(pcr, 0x524A, IC_VER_A)) {
> > +		rtsx_pci_write_phy_register(pcr, PHY_SSCCR3,
> > +			PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY);
> > +		rtsx_pci_write_phy_register(pcr, PHY_SSCCR2,
> > +			PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 |
> > +			PHY_SSCCR2_TIME2_WIDTH);
> > +		rtsx_pci_write_phy_register(pcr, PHY_ANA1A,
> > +			PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST |
> > +			PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV);
> > +		rtsx_pci_write_phy_register(pcr, PHY_ANA1D,
> > +			PHY_ANA1D_DEBUG_ADDR);
> > +		rtsx_pci_write_phy_register(pcr, PHY_DIG1E,
> > +			PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 |
> > +			PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST |
> > +			PHY_DIG1E_RCLK_TX_EN_KEEP |
> > +			PHY_DIG1E_RCLK_TX_TERM_KEEP |
> > +			PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP |
> > +			PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP |
> > +			PHY_DIG1E_RX_EN_KEEP);
> > +	}
> > +
> > +	rtsx_pci_write_phy_register(pcr, PHY_ANA08,
> > +		PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN |
> > +		PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI);
> > To the uninitiated this function is mostly randomness.  How about some
> > nice comments to illuminate?
> I'm not clear with these setting either, it is used to fix some phy 
> setting, the default phy setting
> it not stable on some special platform, so we have to modify them by driver,
> newer version of chip will change its default value to more stable 
> configure, so some value is
> no need to setting for Version B/C...

That doesn't help me in any way.  Use the datasheet, look-up the
values and insert a nice, succinct explanation of what you're doing
and why it's required please.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2015-02-25  7:21 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-22  7:30 [RESEND PATCH v2 0/9] mfd: rtsx: add support for new rts524A and rts525A micky_ching
2015-01-22  7:30 ` [RESEND PATCH v2 1/9] mfd: rtsx: replace TAB by SPC after #define micky_ching
2015-01-22  7:30 ` [RESEND PATCH v2 2/9] mfd: rtsx: place register address and values togather micky_ching
2015-01-22  7:30 ` [RESEND PATCH v2 3/9] mfd: rtsx: update PETXCFG address micky_ching
2015-01-22  7:30 ` [RESEND PATCH v2 4/9] mfd: rtsx: update driving settings micky_ching
2015-01-22  7:40   ` Joe Perches
2015-01-22  7:30 ` [RESEND PATCH v2 5/9] mfd: rtsx: update phy register micky_ching
2015-02-16 14:07   ` Lee Jones
2015-01-22  7:30 ` [RESEND PATCH v2 6/9] mfd: rtsx: remove LCTLR defination micky_ching
2015-02-16 14:31   ` Lee Jones
2015-01-22  7:30 ` [RESEND PATCH v2 7/9] mfd: rtsx: add support for rts524A micky_ching
2015-02-02  1:07   ` 敬锐
2015-02-02  8:52     ` Lee Jones
2015-02-16 14:28   ` Lee Jones
2015-02-25  3:27     ` 敬锐
2015-02-25  7:21       ` Lee Jones
2015-01-22  7:30 ` [RESEND PATCH v2 8/9] mfd: rtsx: add support for rts525A micky_ching
2015-02-16 14:37   ` Lee Jones
2015-01-22  7:30 ` [RESEND PATCH v2 9/9] mfd: rtsx: using pcr_dbg replace dev_dbg micky_ching

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