From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36A53C282E3 for ; Sun, 26 May 2019 23:59:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F3BD521734 for ; Sun, 26 May 2019 23:59:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726034AbfEZX7t (ORCPT ); Sun, 26 May 2019 19:59:49 -0400 Received: from foss.arm.com ([217.140.101.70]:51986 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725846AbfEZX7s (ORCPT ); Sun, 26 May 2019 19:59:48 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 110AC374; Sun, 26 May 2019 16:59:48 -0700 (PDT) Received: from [192.168.3.111] (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B67E63F5AF; Sun, 26 May 2019 16:59:45 -0700 (PDT) Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox To: Sudeep Holla , Florian Fainelli Cc: Peng Fan , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "jassisinghbrar@gmail.com" , "devicetree@vger.kernel.org" , "shawnguo@kernel.org" , "linux-kernel@vger.kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , "van.freenix@gmail.com" , "festevam@gmail.com" , "linux-arm-kernel@lists.infradead.org" References: <20190523060437.11059-1-peng.fan@nxp.com> <4ba2b243-5622-bb27-6fc3-cd9457430e54@gmail.com> <20190524175658.GA5045@e107155-lin> From: =?UTF-8?Q?Andr=c3=a9_Przywara?= Openpgp: preference=signencrypt Autocrypt: addr=andre.przywara@arm.com; prefer-encrypt=mutual; keydata= mQINBFNPCKMBEAC+6GVcuP9ri8r+gg2fHZDedOmFRZPtcrMMF2Cx6KrTUT0YEISsqPoJTKld tPfEG0KnRL9CWvftyHseWTnU2Gi7hKNwhRkC0oBL5Er2hhNpoi8x4VcsxQ6bHG5/dA7ctvL6 kYvKAZw4X2Y3GTbAZIOLf+leNPiF9175S8pvqMPi0qu67RWZD5H/uT/TfLpvmmOlRzNiXMBm kGvewkBpL3R2clHquv7pB6KLoY3uvjFhZfEedqSqTwBVu/JVZZO7tvYCJPfyY5JG9+BjPmr+ REe2gS6w/4DJ4D8oMWKoY3r6ZpHx3YS2hWZFUYiCYovPxfj5+bOr78sg3JleEd0OB0yYtzTT esiNlQpCo0oOevwHR+jUiaZevM4xCyt23L2G+euzdRsUZcK/M6qYf41Dy6Afqa+PxgMEiDto ITEH3Dv+zfzwdeqCuNU0VOGrQZs/vrKOUmU/QDlYL7G8OIg5Ekheq4N+Ay+3EYCROXkstQnf YYxRn5F1oeVeqoh1LgGH7YN9H9LeIajwBD8OgiZDVsmb67DdF6EQtklH0ycBcVodG1zTCfqM AavYMfhldNMBg4vaLh0cJ/3ZXZNIyDlV372GmxSJJiidxDm7E1PkgdfCnHk+pD8YeITmSNyb 7qeU08Hqqh4ui8SSeUp7+yie9zBhJB5vVBJoO5D0MikZAODIDwARAQABtC1BbmRyZSBQcnp5 d2FyYSAoQVJNKSA8YW5kcmUucHJ6eXdhcmFAYXJtLmNvbT6JAjsEEwECACUCGwMGCwkIBwMC BhUIAgkKCwQWAgMBAh4BAheABQJTWSV8AhkBAAoJEAL1yD+ydue63REP/1tPqTo/f6StS00g NTUpjgVqxgsPWYWwSLkgkaUZn2z9Edv86BLpqTY8OBQZ19EUwfNehcnvR+Olw+7wxNnatyxo D2FG0paTia1SjxaJ8Nx3e85jy6l7N2AQrTCFCtFN9lp8Pc0LVBpSbjmP+Peh5Mi7gtCBNkpz KShEaJE25a/+rnIrIXzJHrsbC2GwcssAF3bd03iU41J1gMTalB6HCtQUwgqSsbG8MsR/IwHW XruOnVp0GQRJwlw07e9T3PKTLj3LWsAPe0LHm5W1Q+euoCLsZfYwr7phQ19HAxSCu8hzp43u zSw0+sEQsO+9wz2nGDgQCGepCcJR1lygVn2zwRTQKbq7Hjs+IWZ0gN2nDajScuR1RsxTE4WR lj0+Ne6VrAmPiW6QqRhliDO+e82riI75ywSWrJb9TQw0+UkIQ2DlNr0u0TwCUTcQNN6aKnru ouVt3qoRlcD5MuRhLH+ttAcmNITMg7GQ6RQajWrSKuKFrt6iuDbjgO2cnaTrLbNBBKPTG4oF D6kX8Zea0KvVBagBsaC1CDTDQQMxYBPDBSlqYCb/b2x7KHTvTAHUBSsBRL6MKz8wwruDodTM 4E4ToV9URl4aE/msBZ4GLTtEmUHBh4/AYwk6ACYByYKyx5r3PDG0iHnJ8bV0OeyQ9ujfgBBP B2t4oASNnIOeGEEcQ2rjuQINBFNPCKMBEACm7Xqafb1Dp1nDl06aw/3O9ixWsGMv1Uhfd2B6 it6wh1HDCn9HpekgouR2HLMvdd3Y//GG89irEasjzENZPsK82PS0bvkxxIHRFm0pikF4ljIb 6tca2sxFr/H7CCtWYZjZzPgnOPtnagN0qVVyEM7L5f7KjGb1/o5EDkVR2SVSSjrlmNdTL2Rd zaPqrBoxuR/y/n856deWqS1ZssOpqwKhxT1IVlF6S47CjFJ3+fiHNjkljLfxzDyQXwXCNoZn BKcW9PvAMf6W1DGASoXtsMg4HHzZ5fW+vnjzvWiC4pXrcP7Ivfxx5pB+nGiOfOY+/VSUlW/9 GdzPlOIc1bGyKc6tGREH5lErmeoJZ5k7E9cMJx+xzuDItvnZbf6RuH5fg3QsljQy8jLlr4S6 8YwxlObySJ5K+suPRzZOG2+kq77RJVqAgZXp3Zdvdaov4a5J3H8pxzjj0yZ2JZlndM4X7Msr P5tfxy1WvV4Km6QeFAsjcF5gM+wWl+mf2qrlp3dRwniG1vkLsnQugQ4oNUrx0ahwOSm9p6kM CIiTITo+W7O9KEE9XCb4vV0ejmLlgdDV8ASVUekeTJkmRIBnz0fa4pa1vbtZoi6/LlIdAEEt PY6p3hgkLLtr2GRodOW/Y3vPRd9+rJHq/tLIfwc58ZhQKmRcgrhtlnuTGTmyUqGSiMNfpwAR AQABiQIfBBgBAgAJBQJTTwijAhsMAAoJEAL1yD+ydue64BgP/33QKczgAvSdj9XTC14wZCGE U8ygZwkkyNf021iNMj+o0dpLU48PIhHIMTXlM2aiiZlPWgKVlDRjlYuc9EZqGgbOOuR/pNYA JX9vaqszyE34JzXBL9DBKUuAui8z8GcxRcz49/xtzzP0kH3OQbBIqZWuMRxKEpRptRT0wzBL O31ygf4FRxs68jvPCuZjTGKELIo656/Hmk17cmjoBAJK7JHfqdGkDXk5tneeHCkB411p9WJU vMO2EqsHjobjuFm89hI0pSxlUoiTL0Nuk9Edemjw70W4anGNyaQtBq+qu1RdjUPBvoJec7y/ EXJtoGxq9Y+tmm22xwApSiIOyMwUi9A1iLjQLmngLeUdsHyrEWTbEYHd2sAM2sqKoZRyBDSv ejRvZD6zwkY/9nRqXt02H1quVOP42xlkwOQU6gxm93o/bxd7S5tEA359Sli5gZRaucpNQkwd KLQdCvFdksD270r4jU/rwR2R/Ubi+txfy0dk2wGBjl1xpSf0Lbl/KMR5TQntELfLR4etizLq Xpd2byn96Ivi8C8u9zJruXTueHH8vt7gJ1oax3yKRGU5o2eipCRiKZ0s/T7fvkdq+8beg9ku fDO4SAgJMIl6H5awliCY2zQvLHysS/Wb8QuB09hmhLZ4AifdHyF1J5qeePEhgTA+BaUbiUZf i4aIXCH3Wv6K Organization: ARM Ltd. Message-ID: Date: Mon, 27 May 2019 00:59:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190524175658.GA5045@e107155-lin> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 24/05/2019 18:56, Sudeep Holla wrote: > On Thu, May 23, 2019 at 10:30:50AM -0700, Florian Fainelli wrote: Hi, >> On 5/22/19 10:50 PM, Peng Fan wrote: >>> This is a modified version from Andre Przywara's patch series >>> https://lore.kernel.org/patchwork/cover/812997/. >>> [1] is a draft implementation of i.MX8MM SCMI ATF implementation that >>> use smc as mailbox, power/clk is included, but only part of clk has been >>> implemented to work with hardware, power domain only supports get name >>> for now. >>> >>> The traditional Linux mailbox mechanism uses some kind of dedicated hardware >>> IP to signal a condition to some other processing unit, typically a dedicated >>> management processor. >>> This mailbox feature is used for instance by the SCMI protocol to signal a >>> request for some action to be taken by the management processor. >>> However some SoCs does not have a dedicated management core to provide >>> those services. In order to service TEE and to avoid linux shutdown >>> power and clock that used by TEE, need let firmware to handle power >>> and clock, the firmware here is ARM Trusted Firmware that could also >>> run SCMI service. >>> >>> The existing SCMI implementation uses a rather flexible shared memory >>> region to communicate commands and their parameters, it still requires a >>> mailbox to actually trigger the action. >> >> We have had something similar done internally with a couple of minor >> differences: >> >> - a SGI is used to send SCMI notifications/delayed replies to support >> asynchronism (patches are in the works to actually add that to the Linux >> SCMI framework). There is no good support for SGI in the kernel right >> now so we hacked up something from the existing SMP code and adding the >> ability to register our own IPI handlers (SHAME!). Using a PPI should >> work and should allow for using request_irq() AFAICT. >> > > We have been thinking this since we were asked if SMC can be transport. > Generally out of 16 SGIs, 8 are reserved for secure side and non-secure > has 8. Of these 8, IIUC 7 is already being used by kernel. So unless we > manage to get the last one reserved exclusive to SCMI, it makes it > difficult to add SGI support in SCMI. > > We have been telling partners/vendors about this limitation if they > use SMC as transport and need to have dedicated h/w interrupt for the > notifications. > > Another issue could be with virtualisation(using HVC) and EL handling > so called SCMI SGI. We need to think about those too. I will try to get > more info on this and come back on this. I think regardless of the *current* feasibility of using SGIs in *Linux* we should at least specify an "interrupts" property in the binding, to allow for future usage. We might copy the pmuv3 way [1] of allowing to specify multiple SPI interrupts as well, to give more flexibility. After all an implementation could offload the asynchronous notification to a separate core, and that could use SPIs, for instance. Cheers, Andre. [1] Documentation/devicetree/bindings/arm/pmu.yaml:45