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* [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json
@ 2021-10-04 16:00 Andrew Kilroy
  2021-10-04 16:00 ` [PATCH 2/4] perf vendor events: Add new armv8 pmu events Andrew Kilroy
                   ` (3 more replies)
  0 siblings, 4 replies; 15+ messages in thread
From: Andrew Kilroy @ 2021-10-04 16:00 UTC (permalink / raw)
  To: linux-kernel, linux-perf-users, acme
  Cc: Andrew Kilroy, John Garry, Will Deacon, Mathieu Poirier, Leo Yan,
	Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
	linux-arm-kernel

There are some syntactical mistakes in the json files for the Cortex A76
N1 (Neoverse N1).  This was obstructing parsing from an external tool.

This patch fixes the erroneous placement of commas causing the problems.

Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
---
 .../arch/arm64/arm/cortex-a76-n1/branch.json  |  4 +--
 .../arch/arm64/arm/cortex-a76-n1/bus.json     | 12 +++----
 .../arch/arm64/arm/cortex-a76-n1/cache.json   | 34 +++++++++----------
 .../arm64/arm/cortex-a76-n1/exception.json    |  4 +--
 .../arm64/arm/cortex-a76-n1/instruction.json  | 18 +++++-----
 .../arch/arm64/arm/cortex-a76-n1/memory.json  |  2 +-
 .../arch/arm64/arm/cortex-a76-n1/other.json   |  2 +-
 .../arm64/arm/cortex-a76-n1/pipeline.json     |  4 +--
 8 files changed, 40 insertions(+), 40 deletions(-)

diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
index ec0dc92288ab..db68de188390 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
@@ -1,10 +1,10 @@
 [
     {
         "PublicDescription": "This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken",
-        "ArchStdEvent": "BR_MIS_PRED",
+        "ArchStdEvent": "BR_MIS_PRED"
     },
     {
         "PublicDescription": "This event counts all predictable branches.",
-        "ArchStdEvent": "BR_PRED",
+        "ArchStdEvent": "BR_PRED"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json
index 6263929efce2..e0875d3a685d 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json
@@ -1,21 +1,21 @@
 [
     {
-        "PublicDescription": "The number of core clock cycles"
+        "PublicDescription": "The number of core clock cycles",
         "ArchStdEvent": "CPU_CYCLES",
         "BriefDescription": "The number of core clock cycles."
     },
     {
         "PublicDescription": "This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR.",
-        "ArchStdEvent": "BUS_ACCESS",
+        "ArchStdEvent": "BUS_ACCESS"
     },
     {
-        "PublicDescription": "This event duplicates CPU_CYCLES."
-        "ArchStdEvent": "BUS_CYCLES",
+        "PublicDescription": "This event duplicates CPU_CYCLES.",
+        "ArchStdEvent": "BUS_CYCLES"
     },
     {
-        "ArchStdEvent":  "BUS_ACCESS_RD",
+        "ArchStdEvent":  "BUS_ACCESS_RD"
     },
     {
-        "ArchStdEvent":  "BUS_ACCESS_WR",
+        "ArchStdEvent":  "BUS_ACCESS_WR"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json
index cd67bb9df139..fc448c2d5ea4 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json
@@ -1,47 +1,47 @@
 [
     {
         "PublicDescription": "This event counts any instruction fetch which misses in the cache.",
-        "ArchStdEvent": "L1I_CACHE_REFILL",
+        "ArchStdEvent": "L1I_CACHE_REFILL"
     },
     {
         "PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes refills that result in a translation fault.",
-        "ArchStdEvent": "L1I_TLB_REFILL",
+        "ArchStdEvent": "L1I_TLB_REFILL"
     },
     {
         "PublicDescription": "This event counts any load or store operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1.",
-        "ArchStdEvent": "L1D_CACHE_REFILL",
+        "ArchStdEvent": "L1D_CACHE_REFILL"
     },
     {
         "PublicDescription": "This event counts any load or store operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL event causes this event to count.",
-        "ArchStdEvent": "L1D_CACHE",
+        "ArchStdEvent": "L1D_CACHE"
     },
     {
         "PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includes refills that result in a translation fault.",
-        "ArchStdEvent": "L1D_TLB_REFILL",
+        "ArchStdEvent": "L1D_TLB_REFILL"
     },
-    {,
+    {
         "PublicDescription": "Level 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 instruction cache or L0 Macro-op cache.",
-        "ArchStdEvent": "L1I_CACHE",
+        "ArchStdEvent": "L1I_CACHE"
     },
     {
         "PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line evictions and snoops, including cache maintenance operations.",
-        "ArchStdEvent": "L1D_CACHE_WB",
+        "ArchStdEvent": "L1D_CACHE_WB"
     },
     {
         "PublicDescription": "This event counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted.",
-        "ArchStdEvent": "L2D_CACHE",
+        "ArchStdEvent": "L2D_CACHE"
     },
     {
         "PublicDescription": "L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted",
-        "ArchStdEvent": "L2D_CACHE_REFILL",
+        "ArchStdEvent": "L2D_CACHE_REFILL"
     },
     {
         "PublicDescription": "This event counts any write-back of data from the L2 cache to outside the core. This includes snoops to the L2 which return data, regardless of whether they cause an invalidation. Invalidations from the L2 which do not write data outside of the core and snoops which return data from the L1 are not counted",
-        "ArchStdEvent": "L2D_CACHE_WB",
+        "ArchStdEvent": "L2D_CACHE_WB"
     },
     {
         "PublicDescription": "This event counts any full cache line write into the L2 cache which does not cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate into L1.",
-        "ArchStdEvent": "L2D_CACHE_ALLOCATE",
+        "ArchStdEvent": "L2D_CACHE_ALLOCATE"
     },
     {
         "PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB. If both a load and a store are executed on a cycle, this event counts twice. This event counts regardless of whether the MMU is enabled.",
@@ -75,21 +75,21 @@
     },
     {
         "PublicDescription": "This event counts on any access to the L2 TLB (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabled.",
-        "ArchStdEvent": "L2D_TLB",
+        "ArchStdEvent": "L2D_TLB"
     },
     {
         "PublicDescription": "This event counts on any data access which causes L2D_TLB_REFILL to count.",
-        "ArchStdEvent": "DTLB_WALK",
+        "ArchStdEvent": "DTLB_WALK"
     },
     {
         "PublicDescription": "This event counts on any instruction access which causes L2D_TLB_REFILL to count.",
-        "ArchStdEvent": "ITLB_WALK",
+        "ArchStdEvent": "ITLB_WALK"
     },
     {
-        "ArchStdEvent": "LL_CACHE_RD",
+        "ArchStdEvent": "LL_CACHE_RD"
     },
     {
-        "ArchStdEvent": "LL_CACHE_MISS_RD",
+        "ArchStdEvent": "LL_CACHE_MISS_RD"
     },
     {
         "ArchStdEvent": "L1D_CACHE_INVAL"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json
index ea4631db41b5..ce942324ee60 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json
@@ -1,10 +1,10 @@
 [
     {
-        "ArchStdEvent": "EXC_TAKEN",
+        "ArchStdEvent": "EXC_TAKEN"
     },
     {
         "PublicDescription": "This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
-        "ArchStdEvent": "MEMORY_ERROR",
+        "ArchStdEvent": "MEMORY_ERROR"
     },
     {
         "ArchStdEvent": "EXC_DABORT"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json
index 8e59566cba8b..b0b439a36ae9 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json
@@ -1,32 +1,32 @@
 [
     {
-        "ArchStdEvent": "SW_INCR",
+        "ArchStdEvent": "SW_INCR"
     },
     {
         "PublicDescription": "This event counts all retired instructions, including those that fail their condition check.",
-        "ArchStdEvent": "INST_RETIRED",
+        "ArchStdEvent": "INST_RETIRED"
     },
     {
-        "ArchStdEvent": "EXC_RETURN",
+        "ArchStdEvent": "EXC_RETURN"
     },
     {
         "PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.",
-        "ArchStdEvent": "CID_WRITE_RETIRED",
+        "ArchStdEvent": "CID_WRITE_RETIRED"
     },
     {
-        "ArchStdEvent": "INST_SPEC",
+        "ArchStdEvent": "INST_SPEC"
     },
     {
         "PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.",
-        "ArchStdEvent": "TTBR_WRITE_RETIRED",
+        "ArchStdEvent": "TTBR_WRITE_RETIRED"
     },
-    {,
+    {
         "PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches.",
-        "ArchStdEvent": "BR_RETIRED",
+        "ArchStdEvent": "BR_RETIRED"
     },
     {
         "PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush.",
-        "ArchStdEvent": "BR_MIS_PRED_RETIRED",
+        "ArchStdEvent": "BR_MIS_PRED_RETIRED"
     },
     {
         "ArchStdEvent": "ASE_SPEC"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json
index f06f399051c1..20a929e7728d 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json
@@ -1,7 +1,7 @@
 [
     {
         "PublicDescription": "This event counts memory accesses due to load or store instructions. This event counts the sum of MEM_ACCESS_RD and MEM_ACCESS_WR.",
-        "ArchStdEvent": "MEM_ACCESS",
+        "ArchStdEvent": "MEM_ACCESS"
     },
     {
          "ArchStdEvent": "MEM_ACCESS_RD"
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/other.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/other.json
index c2ccbf6fbfa0..20d8365756c5 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/other.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/other.json
@@ -1,5 +1,5 @@
 [
     {
-        "ArchStdEvent": "REMOTE_ACCESS",
+        "ArchStdEvent": "REMOTE_ACCESS"
     }
 ]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json
index d79f0aeaf7f1..b4e96551d51a 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json
@@ -1,10 +1,10 @@
 [
     {
         "PublicDescription": "The counter counts on any cycle when there are no fetched instructions available to dispatch.",
-        "ArchStdEvent": "STALL_FRONTEND",
+        "ArchStdEvent": "STALL_FRONTEND"
     },
     {
         "PublicDescription": "The counter counts on any cycle fetched instructions are not dispatched due to resource constraints.",
-        "ArchStdEvent": "STALL_BACKEND",
+        "ArchStdEvent": "STALL_BACKEND"
     }
 ]
-- 
2.17.1


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH 2/4] perf vendor events: Add new armv8 pmu events
  2021-10-04 16:00 [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json Andrew Kilroy
@ 2021-10-04 16:00 ` Andrew Kilroy
  2021-10-05 10:01   ` John Garry
  2021-10-04 16:00 ` [PATCH 3/4] perf vendor events: Categorise the Neoverse V1 counters Andrew Kilroy
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 15+ messages in thread
From: Andrew Kilroy @ 2021-10-04 16:00 UTC (permalink / raw)
  To: linux-kernel, linux-perf-users, acme
  Cc: Andrew Kilroy, John Garry, Will Deacon, Mathieu Poirier, Leo Yan,
	Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
	linux-arm-kernel

Add new armv8 common events for use by Arm Neoverse V1 cores in a later
commit. These are defined in the ArmV8 architecture reference manual
available from

  https://developer.arm.com/documentation/ddi0487/gb/?lang=en

Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
---
 .../arm64/armv8-common-and-microarch.json     | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json b/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json
index 913fb200ea52..423767510aff 100644
--- a/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json
+++ b/tools/perf/pmu-events/arch/arm64/armv8-common-and-microarch.json
@@ -257,6 +257,78 @@
         "EventName": "LL_CACHE_MISS_RD",
         "BriefDescription": "Last level cache miss, read"
     },
+    {
+        "PublicDescription": "Level 1 data cache long-latency read miss.  The counter counts each memory read access counted by L1D_CACHE that incurs additional latency because it returns data from outside the Level 1 data or unified cache of this processing element.",
+        "EventCode": "0x39",
+        "EventName": "L1D_CACHE_LMISS_RD",
+        "BriefDescription": "Level 1 data cache long-latency read miss"
+    },
+    {
+        "PublicDescription": "Micro-operation architecturally executed.  The counter counts each operation counted by OP_SPEC that would be executed in a simple sequential execution of the program.",
+        "EventCode": "0x3A",
+        "EventName": "OP_RETIRED",
+        "BriefDescription": "Micro-operation architecturally executed"
+    },
+    {
+        "PublicDescription": "Micro-operation speculatively executed.  The counter counts the number of operations executed by the processing element, including those that are executed speculatively and would not be executed in a simple sequential execution of the program.",
+        "EventCode": "0x3B",
+        "EventName": "OP_SPEC",
+        "BriefDescription": "Micro-operation speculatively executed"
+    },
+    {
+        "PublicDescription": "No operation sent for execution.  The counter counts every attributable cycle on which no attributable instruction or operation was sent for execution on this processing element.",
+        "EventCode": "0x3C",
+        "EventName": "STALL",
+        "BriefDescription": "No operation sent for execution"
+    },
+    {
+        "PublicDescription": "No operation sent for execution on a slot due to the backend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because the backend is unable to accept it.",
+        "EventCode": "0x3D",
+        "EventName": "STALL_SLOT_BACKEND",
+        "BriefDescription": "No operation sent for execution on a slot due to the backend"
+    },
+    {
+        "PublicDescription": "No operation sent for execution on a slot due to the frontend.  Counts each slot counted by STALL_SLOT where no attributable instruction or operation was sent for execution because there was no attributable instruction or operation available to issue from the processing element from the frontend for the slot.",
+        "EventCode": "0x3E",
+        "EventName": "STALL_SLOT_FRONTEND",
+        "BriefDescription": "No operation sent for execution on a slot due to the frontend"
+    },
+    {
+        "PublicDescription": "No operation sent for execution on a slot.  The counter counts on each attributable cycle the number of instruction or operation slots that were not occupied by an instruction or operation attributable to the processing element.",
+        "EventCode": "0x3F",
+        "EventName": "STALL_SLOT",
+        "BriefDescription": "No operation sent for execution on a slot"
+    },
+    {
+        "PublicDescription": "Constant frequency cycles.  The counter increments at a constant frequency equal to the rate of increment of the system counter, CNTPCT_EL0.",
+        "EventCode": "0x4004",
+        "EventName": "CNT_CYCLES",
+        "BriefDescription": "Constant frequency cycles"
+    },
+    {
+        "PublicDescription": "Memory stall cycles.  The counter counts each cycle counted by STALL_BACKEND where there is a cache miss in the last level of cache within the processing element clock domain",
+        "EventCode": "0x4005",
+        "EventName": "STALL_BACKEND_MEM",
+        "BriefDescription": "Memory stall cycles"
+    },
+    {
+        "PublicDescription": "Level 1 instruction cache long-latency read miss.  If the L1I_CACHE_RD event is implemented, the counter counts each access counted by L1I_CACHE_RD that incurs additional latency because it returns instructions from outside of the Level 1 instruction cache of this PE.  If the L1I_CACHE_RD event is not implemented, the counter counts each access counted by L1I_CACHE that incurs additional latency because it returns instructions from outside the Level 1 instruction cache of this PE.  The event indicates to software that the access missed in the Level 1 instruction cache and might have a significant performance impact due to the additional latency, compared to the latency of an access that hits in the Level 1 instruction cache.",
+        "EventCode": "0x4006",
+        "EventName": "L1I_CACHE_LMISS",
+        "BriefDescription": "Level 1 instruction cache long-latency read miss"
+    },
+    {
+        "PublicDescription": "Level 2 data cache long-latency read miss.  The counter counts each memory read access counted by L2D_CACHE that incurs additional latency because it returns data from outside the Level 2 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 2 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 2 data or unified cache.",
+        "EventCode": "0x4009",
+        "EventName": "L2D_CACHE_LMISS_RD",
+        "BriefDescription": "Level 2 data cache long-latency read miss"
+    },
+    {
+        "PublicDescription": "Level 3 data cache long-latency read miss.  The counter counts each memory read access counted by L3D_CACHE that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this processing element.  The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache.",
+        "EventCode": "0x400B",
+        "EventName": "L3D_CACHE_LMISS_RD",
+        "BriefDescription": "Level 3 data cache long-latency read miss"
+    },
     {
         "PublicDescription": "SIMD Instruction architecturally executed.",
         "EventCode": "0x8000",
-- 
2.17.1


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH 3/4] perf vendor events: Categorise the Neoverse V1 counters
  2021-10-04 16:00 [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json Andrew Kilroy
  2021-10-04 16:00 ` [PATCH 2/4] perf vendor events: Add new armv8 pmu events Andrew Kilroy
@ 2021-10-04 16:00 ` Andrew Kilroy
  2021-10-04 16:00 ` [PATCH 4/4] perf vendor events: Add the Neoverse V1 to arm64 mapfile Andrew Kilroy
  2021-10-05 10:10 ` [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json John Garry
  3 siblings, 0 replies; 15+ messages in thread
From: Andrew Kilroy @ 2021-10-04 16:00 UTC (permalink / raw)
  To: linux-kernel, linux-perf-users, acme
  Cc: Andrew Kilroy, John Garry, Will Deacon, Mathieu Poirier, Leo Yan,
	Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
	linux-arm-kernel

This is so they are categorised in the perf list output.  The pmus all
exist in the armv8-common-and-microarch.json and arm-recommended.json
files, so this commit places them into each category's own file under

  tools/perf/pmu-events/arch/arm64/arm/neoverse-v1

Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
---
 .../arch/arm64/arm/neoverse-v1/branch.json    |   8 +
 .../arch/arm64/arm/neoverse-v1/bus.json       |  20 +++
 .../arch/arm64/arm/neoverse-v1/cache.json     | 155 ++++++++++++++++++
 .../arch/arm64/arm/neoverse-v1/exception.json |  47 ++++++
 .../arm64/arm/neoverse-v1/instruction.json    |  89 ++++++++++
 .../arch/arm64/arm/neoverse-v1/memory.json    |  20 +++
 .../arch/arm64/arm/neoverse-v1/other.json     |   5 +
 .../arch/arm64/arm/neoverse-v1/pipeline.json  |  23 +++
 8 files changed, 367 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/exception.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/other.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/pipeline.json

diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/branch.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/branch.json
new file mode 100644
index 000000000000..79f2016c53b0
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/branch.json
@@ -0,0 +1,8 @@
+[
+    {
+        "ArchStdEvent": "BR_MIS_PRED"
+    },
+    {
+        "ArchStdEvent": "BR_PRED"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/bus.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/bus.json
new file mode 100644
index 000000000000..579c1c993d17
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/bus.json
@@ -0,0 +1,20 @@
+[
+    {
+        "ArchStdEvent": "CPU_CYCLES"
+    },
+    {
+        "ArchStdEvent": "BUS_ACCESS"
+    },
+    {
+        "ArchStdEvent": "BUS_CYCLES"
+    },
+    {
+        "ArchStdEvent": "BUS_ACCESS_RD"
+    },
+    {
+        "ArchStdEvent": "BUS_ACCESS_WR"
+    },
+    {
+        "ArchStdEvent": "CNT_CYCLES"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/cache.json
new file mode 100644
index 000000000000..0141f749bff3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/cache.json
@@ -0,0 +1,155 @@
+[
+    {
+        "ArchStdEvent": "L1I_CACHE_REFILL"
+    },
+    {
+        "ArchStdEvent": "L1I_TLB_REFILL"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE"
+    },
+    {
+        "ArchStdEvent": "L1D_TLB_REFILL"
+    },
+    {
+        "ArchStdEvent": "L1I_CACHE"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WB"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_REFILL"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_WB"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_ALLOCATE"
+    },
+    {
+        "ArchStdEvent": "L1D_TLB"
+    },
+    {
+        "ArchStdEvent": "L1I_TLB"
+    },
+    {
+        "ArchStdEvent": "L3D_CACHE_ALLOCATE"
+    },
+    {
+        "ArchStdEvent": "L3D_CACHE_REFILL"
+    },
+    {
+        "ArchStdEvent": "L3D_CACHE"
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_REFILL"
+    },
+    {
+        "ArchStdEvent": "L2D_TLB"
+    },
+    {
+        "ArchStdEvent": "DTLB_WALK"
+    },
+    {
+        "ArchStdEvent": "ITLB_WALK"
+    },
+    {
+        "ArchStdEvent": "LL_CACHE_RD"
+    },
+    {
+        "ArchStdEvent": "LL_CACHE_MISS_RD"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_LMISS_RD"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_RD"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WR"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_INVAL"
+    },
+    {
+        "ArchStdEvent": "L1D_TLB_REFILL_RD"
+    },
+    {
+        "ArchStdEvent": "L1D_TLB_REFILL_WR"
+    },
+    {
+        "ArchStdEvent": "L1D_TLB_RD"
+    },
+    {
+        "ArchStdEvent": "L1D_TLB_WR"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_RD"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_WR"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_INVAL"
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_REFILL_RD"
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_REFILL_WR"
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_RD"
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_WR"
+    },
+    {
+        "ArchStdEvent": "L3D_CACHE_RD"
+    },
+    {
+        "ArchStdEvent": "L1I_CACHE_LMISS"
+    },
+    {
+        "ArchStdEvent": "L2D_CACHE_LMISS_RD"
+    },
+    {
+        "ArchStdEvent": "L3D_CACHE_LMISS_RD"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/exception.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/exception.json
new file mode 100644
index 000000000000..344a2d552ad5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/exception.json
@@ -0,0 +1,47 @@
+[
+    {
+        "ArchStdEvent": "EXC_TAKEN"
+    },
+    {
+        "ArchStdEvent": "MEMORY_ERROR"
+    },
+    {
+        "ArchStdEvent": "EXC_UNDEF"
+    },
+    {
+        "ArchStdEvent": "EXC_SVC"
+    },
+    {
+        "ArchStdEvent": "EXC_PABORT"
+    },
+    {
+        "ArchStdEvent": "EXC_DABORT"
+    },
+    {
+        "ArchStdEvent": "EXC_IRQ"
+    },
+    {
+        "ArchStdEvent": "EXC_FIQ"
+    },
+    {
+        "ArchStdEvent": "EXC_SMC"
+    },
+    {
+        "ArchStdEvent": "EXC_HVC"
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_PABORT"
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_DABORT"
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_OTHER"
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_IRQ"
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_FIQ"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/instruction.json
new file mode 100644
index 000000000000..25825e14c535
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/instruction.json
@@ -0,0 +1,89 @@
+[
+    {
+        "ArchStdEvent": "SW_INCR"
+    },
+    {
+        "ArchStdEvent": "INST_RETIRED"
+    },
+    {
+        "ArchStdEvent": "EXC_RETURN"
+    },
+    {
+        "ArchStdEvent": "CID_WRITE_RETIRED"
+    },
+    {
+        "ArchStdEvent": "INST_SPEC"
+    },
+    {
+        "ArchStdEvent": "TTBR_WRITE_RETIRED"
+    },
+    {
+        "ArchStdEvent": "BR_RETIRED"
+    },
+    {
+        "ArchStdEvent": "BR_MIS_PRED_RETIRED"
+    },
+    {
+        "ArchStdEvent": "OP_RETIRED"
+    },
+    {
+        "ArchStdEvent": "OP_SPEC"
+    },
+    {
+        "ArchStdEvent": "LDREX_SPEC"
+    },
+    {
+        "ArchStdEvent": "STREX_PASS_SPEC"
+    },
+    {
+        "ArchStdEvent": "STREX_FAIL_SPEC"
+    },
+    {
+        "ArchStdEvent": "STREX_SPEC"
+    },
+    {
+        "ArchStdEvent": "LD_SPEC"
+    },
+    {
+        "ArchStdEvent": "ST_SPEC"
+    },
+    {
+        "ArchStdEvent": "DP_SPEC"
+    },
+    {
+        "ArchStdEvent": "ASE_SPEC"
+    },
+    {
+        "ArchStdEvent": "VFP_SPEC"
+    },
+    {
+        "ArchStdEvent": "PC_WRITE_SPEC"
+    },
+    {
+        "ArchStdEvent": "CRYPTO_SPEC"
+    },
+    {
+        "ArchStdEvent": "BR_IMMED_SPEC"
+    },
+    {
+        "ArchStdEvent": "BR_RETURN_SPEC"
+    },
+    {
+        "ArchStdEvent": "BR_INDIRECT_SPEC"
+    },
+    {
+        "ArchStdEvent": "ISB_SPEC"
+    },
+    {
+        "ArchStdEvent": "DSB_SPEC"
+    },
+    {
+        "ArchStdEvent": "DMB_SPEC"
+    },
+    {
+        "ArchStdEvent": "RC_LD_SPEC"
+    },
+    {
+        "ArchStdEvent": "RC_ST_SPEC"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/memory.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/memory.json
new file mode 100644
index 000000000000..e3d08f1f7c92
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/memory.json
@@ -0,0 +1,20 @@
+[
+    {
+        "ArchStdEvent": "MEM_ACCESS"
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS_RD"
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS_WR"
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_LD_SPEC"
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_ST_SPEC"
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_LDST_SPEC"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/other.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/other.json
new file mode 100644
index 000000000000..20d8365756c5
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/other.json
@@ -0,0 +1,5 @@
+[
+    {
+        "ArchStdEvent": "REMOTE_ACCESS"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/pipeline.json
new file mode 100644
index 000000000000..f9fae15f7555
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/pipeline.json
@@ -0,0 +1,23 @@
+[
+    {
+        "ArchStdEvent": "STALL_FRONTEND"
+    },
+    {
+        "ArchStdEvent": "STALL_BACKEND"
+    },
+    {
+        "ArchStdEvent": "STALL"
+    },
+    {
+        "ArchStdEvent": "STALL_SLOT_BACKEND"
+    },
+    {
+        "ArchStdEvent": "STALL_SLOT_FRONTEND"
+    },
+    {
+        "ArchStdEvent": "STALL_SLOT"
+    },
+    {
+        "ArchStdEvent": "STALL_BACKEND_MEM"
+    }
+]
-- 
2.17.1


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH 4/4] perf vendor events: Add the Neoverse V1 to arm64 mapfile
  2021-10-04 16:00 [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json Andrew Kilroy
  2021-10-04 16:00 ` [PATCH 2/4] perf vendor events: Add new armv8 pmu events Andrew Kilroy
  2021-10-04 16:00 ` [PATCH 3/4] perf vendor events: Categorise the Neoverse V1 counters Andrew Kilroy
@ 2021-10-04 16:00 ` Andrew Kilroy
  2021-10-05  9:33   ` John Garry
  2021-10-05 10:10 ` [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json John Garry
  3 siblings, 1 reply; 15+ messages in thread
From: Andrew Kilroy @ 2021-10-04 16:00 UTC (permalink / raw)
  To: linux-kernel, linux-perf-users, acme
  Cc: Andrew Kilroy, John Garry, Will Deacon, Mathieu Poirier, Leo Yan,
	Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
	linux-arm-kernel

This is so that performance counters for the Neoverse V1 appear
categorised upon running 'perf list' on the CPU.

Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
---
 tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index c43591d831b8..31d8b57ca9bb 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -18,6 +18,7 @@
 0x00000000410fd080,v1,arm/cortex-a57-a72,core
 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
+0x00000000410fd400,v1,arm/neoverse-v1,core
 0x00000000420f5160,v1,cavium/thunderx2,core
 0x00000000430f0af0,v1,cavium/thunderx2,core
 0x00000000460f0010,v1,fujitsu/a64fx,core
-- 
2.17.1


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] perf vendor events: Add the Neoverse V1 to arm64 mapfile
  2021-10-04 16:00 ` [PATCH 4/4] perf vendor events: Add the Neoverse V1 to arm64 mapfile Andrew Kilroy
@ 2021-10-05  9:33   ` John Garry
  2021-10-05 17:58     ` Arnaldo Carvalho de Melo
  0 siblings, 1 reply; 15+ messages in thread
From: John Garry @ 2021-10-05  9:33 UTC (permalink / raw)
  To: Andrew Kilroy, linux-kernel, linux-perf-users, acme
  Cc: Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
	Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel

On 04/10/2021 17:00, Andrew Kilroy wrote:
> This is so that performance counters for the Neoverse V1 appear
> categorised upon running 'perf list' on the CPU.
> 

this really belongs with the previous patch

Thanks,
John

> Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
> ---
>   tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> index c43591d831b8..31d8b57ca9bb 100644
> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> @@ -18,6 +18,7 @@
>   0x00000000410fd080,v1,arm/cortex-a57-a72,core
>   0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
>   0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
> +0x00000000410fd400,v1,arm/neoverse-v1,core
>   0x00000000420f5160,v1,cavium/thunderx2,core
>   0x00000000430f0af0,v1,cavium/thunderx2,core
>   0x00000000460f0010,v1,fujitsu/a64fx,core
> 


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 2/4] perf vendor events: Add new armv8 pmu events
  2021-10-04 16:00 ` [PATCH 2/4] perf vendor events: Add new armv8 pmu events Andrew Kilroy
@ 2021-10-05 10:01   ` John Garry
  0 siblings, 0 replies; 15+ messages in thread
From: John Garry @ 2021-10-05 10:01 UTC (permalink / raw)
  To: Andrew Kilroy, linux-kernel, linux-perf-users, acme
  Cc: Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
	Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel

On 04/10/2021 17:00, Andrew Kilroy wrote:
> Add new armv8 common events for use by Arm Neoverse V1 cores in a later
> commit. These are defined in the ArmV8 architecture reference manual
> available from
> 
>    https://developer.arm.com/documentation/ddi0487/gb/?lang=e >
> Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>

Reviewed-by: John Garry <john.garry@huawei.com>

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json
  2021-10-04 16:00 [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json Andrew Kilroy
                   ` (2 preceding siblings ...)
  2021-10-04 16:00 ` [PATCH 4/4] perf vendor events: Add the Neoverse V1 to arm64 mapfile Andrew Kilroy
@ 2021-10-05 10:10 ` John Garry
  2021-10-06  8:43   ` James Clark
  3 siblings, 1 reply; 15+ messages in thread
From: John Garry @ 2021-10-05 10:10 UTC (permalink / raw)
  To: Andrew Kilroy, linux-kernel, linux-perf-users, acme
  Cc: Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
	Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel

On 04/10/2021 17:00, Andrew Kilroy wrote:
> There are some syntactical mistakes in the json files for the Cortex A76
> N1 (Neoverse N1).  This was obstructing parsing from an external tool.

If the trailing comma is not allowed by standard, then maybe we should 
fix our parsing tool to not allow it also. However maybe there is a good 
reason why we allow it..

Reviewed-by: John Garry <john.garry@huawei.com>

> 
> This patch fixes the erroneous placement of commas causing the problems.
> 
> Signed-off-by: Andrew Kilroy<andrew.kilroy@arm.com>
> ---
>   .../arch/arm64/arm/cortex-a76-n1/branch.json  |  4 +--
>   .../arch/arm64/arm/cortex-a76-n1/bus.json     | 12 +++----
>   .../arch/arm64/arm/cortex-a76-n1/cache.json   | 34 +++++++++----------
>   .../arm64/arm/cortex-a76-n1/exception.json    |  4 +--
>   .../arm64/arm/cortex-a76-n1/instruction.json  | 18 +++++-----
>   .../arch/arm64/arm/cortex-a76-n1/memory.json  |  2 +-
>   .../arch/arm64/arm/cortex-a76-n1/other.json   |  2 +-
>   .../arm64/arm/cortex-a76-n1/pipeline.json     |  4 +--
>   8 files changed, 40 insertions(+), 40 deletions(-)
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
> index ec0dc92288ab..db68de188390 100644
> --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
> +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json
> @@ -1,10 +1,10 @@
>   [
>       {
>           "PublicDescription": "This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken",
> -        "ArchStdEvent": "BR_MIS_PRED",
> +        "ArchStdEvent": "BR_MIS_PRED"
>       },


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] perf vendor events: Add the Neoverse V1 to arm64 mapfile
  2021-10-05  9:33   ` John Garry
@ 2021-10-05 17:58     ` Arnaldo Carvalho de Melo
  2021-10-06  8:20       ` Andrew Kilroy
  0 siblings, 1 reply; 15+ messages in thread
From: Arnaldo Carvalho de Melo @ 2021-10-05 17:58 UTC (permalink / raw)
  To: John Garry
  Cc: Andrew Kilroy, linux-kernel, linux-perf-users, Will Deacon,
	Mathieu Poirier, Leo Yan, Mark Rutland, Alexander Shishkin,
	Jiri Olsa, Namhyung Kim, linux-arm-kernel

Em Tue, Oct 05, 2021 at 10:33:49AM +0100, John Garry escreveu:
> On 04/10/2021 17:00, Andrew Kilroy wrote:
> > This is so that performance counters for the Neoverse V1 appear
> > categorised upon running 'perf list' on the CPU.
> > 
> 
> this really belongs with the previous patch

Waiting for a resolution on this one.

- Arnaldo
 
> Thanks,
> John
> 
> > Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
> > ---
> >   tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
> >   1 file changed, 1 insertion(+)
> > 
> > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> > index c43591d831b8..31d8b57ca9bb 100644
> > --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
> > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> > @@ -18,6 +18,7 @@
> >   0x00000000410fd080,v1,arm/cortex-a57-a72,core
> >   0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
> >   0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
> > +0x00000000410fd400,v1,arm/neoverse-v1,core
> >   0x00000000420f5160,v1,cavium/thunderx2,core
> >   0x00000000430f0af0,v1,cavium/thunderx2,core
> >   0x00000000460f0010,v1,fujitsu/a64fx,core
> > 

-- 

- Arnaldo

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] perf vendor events: Add the Neoverse V1 to arm64 mapfile
  2021-10-05 17:58     ` Arnaldo Carvalho de Melo
@ 2021-10-06  8:20       ` Andrew Kilroy
  2021-10-06  8:29         ` Andrew Kilroy
  0 siblings, 1 reply; 15+ messages in thread
From: Andrew Kilroy @ 2021-10-06  8:20 UTC (permalink / raw)
  To: Arnaldo Carvalho de Melo, John Garry
  Cc: linux-kernel, linux-perf-users, Will Deacon, Mathieu Poirier,
	Leo Yan, Mark Rutland, Alexander Shishkin, Jiri Olsa,
	Namhyung Kim, linux-arm-kernel

Hi Arnaldo + John,

On 05/10/2021 18:58, Arnaldo Carvalho de Melo wrote:
> Em Tue, Oct 05, 2021 at 10:33:49AM +0100, John Garry escreveu:
>> On 04/10/2021 17:00, Andrew Kilroy wrote:
>>> This is so that performance counters for the Neoverse V1 appear
>>> categorised upon running 'perf list' on the CPU.
>>>
>>
>> this really belongs with the previous patch
> 
> Waiting for a resolution on this one.
> 
> - Arnaldo
>   
>> Thanks,
>> John
>>

Sent a v2 of these patches

Andrew



>>> Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
>>> ---
>>>    tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
>>>    1 file changed, 1 insertion(+)
>>>
>>> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>> index c43591d831b8..31d8b57ca9bb 100644
>>> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>> @@ -18,6 +18,7 @@
>>>    0x00000000410fd080,v1,arm/cortex-a57-a72,core
>>>    0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
>>>    0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
>>> +0x00000000410fd400,v1,arm/neoverse-v1,core
>>>    0x00000000420f5160,v1,cavium/thunderx2,core
>>>    0x00000000430f0af0,v1,cavium/thunderx2,core
>>>    0x00000000460f0010,v1,fujitsu/a64fx,core
>>>
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 4/4] perf vendor events: Add the Neoverse V1 to arm64 mapfile
  2021-10-06  8:20       ` Andrew Kilroy
@ 2021-10-06  8:29         ` Andrew Kilroy
  0 siblings, 0 replies; 15+ messages in thread
From: Andrew Kilroy @ 2021-10-06  8:29 UTC (permalink / raw)
  To: Arnaldo Carvalho de Melo, John Garry
  Cc: linux-kernel, linux-perf-users, Will Deacon, Mathieu Poirier,
	Leo Yan, Mark Rutland, Alexander Shishkin, Jiri Olsa,
	Namhyung Kim, linux-arm-kernel



On 06/10/2021 09:20, Andrew Kilroy wrote:
> Hi Arnaldo + John,
> 
> On 05/10/2021 18:58, Arnaldo Carvalho de Melo wrote:
>> Em Tue, Oct 05, 2021 at 10:33:49AM +0100, John Garry escreveu:
>>> On 04/10/2021 17:00, Andrew Kilroy wrote:
>>>> This is so that performance counters for the Neoverse V1 appear
>>>> categorised upon running 'perf list' on the CPU.
>>>>
>>>
>>> this really belongs with the previous patch
>>
>> Waiting for a resolution on this one.
>>
>> - Arnaldo
>>> Thanks,
>>> John
>>>
> 
> Sent a v2 of these patches
> 
> Andrew

I forgot to add, thanks for the review!

Andrew


> 
> 
> 
>>>> Signed-off-by: Andrew Kilroy <andrew.kilroy@arm.com>
>>>> ---
>>>>    tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
>>>>    1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv 
>>>> b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>>> index c43591d831b8..31d8b57ca9bb 100644
>>>> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>>> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>>> @@ -18,6 +18,7 @@
>>>>    0x00000000410fd080,v1,arm/cortex-a57-a72,core
>>>>    0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
>>>>    0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
>>>> +0x00000000410fd400,v1,arm/neoverse-v1,core
>>>>    0x00000000420f5160,v1,cavium/thunderx2,core
>>>>    0x00000000430f0af0,v1,cavium/thunderx2,core
>>>>    0x00000000460f0010,v1,fujitsu/a64fx,core
>>>>
>>

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json
  2021-10-05 10:10 ` [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json John Garry
@ 2021-10-06  8:43   ` James Clark
  2021-10-06 16:26     ` John Garry
  0 siblings, 1 reply; 15+ messages in thread
From: James Clark @ 2021-10-06  8:43 UTC (permalink / raw)
  To: John Garry, Andrew Kilroy, linux-kernel, linux-perf-users, acme
  Cc: Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
	Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel



On 05/10/2021 11:10, John Garry wrote:
> On 04/10/2021 17:00, Andrew Kilroy wrote:
>> There are some syntactical mistakes in the json files for the Cortex A76
>> N1 (Neoverse N1).  This was obstructing parsing from an external tool.
> 
> If the trailing comma is not allowed by standard, then maybe we should fix our parsing tool to not allow it also. However maybe there is a good reason why we allow it..

It would be nice to do, because I have also made similar fixes before. We looked at the STRICT option
in the parser (https://github.com/zserge/jsmn), but even then it seems to allow trailing commas.

Trailing commas are not allowed in the json standard, but there is a split between parsers
where some allow it and others don't. Specifically the Python parser doesn't allow it, and Python
can easily be involved in some workflow that parses these files.

The only way forwards I can think of is either getting a change accepted upstream to the parser
and then updating it in perf, switching to a different parser, or doing some hack to add an extra
step in perf to look for commas. None of which sound ideal.

James


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json
  2021-10-06  8:43   ` James Clark
@ 2021-10-06 16:26     ` John Garry
  2021-10-08  0:03       ` Andi Kleen
  0 siblings, 1 reply; 15+ messages in thread
From: John Garry @ 2021-10-06 16:26 UTC (permalink / raw)
  To: James Clark, Andrew Kilroy, linux-kernel, linux-perf-users, acme
  Cc: Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
	Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel,
	Andi Kleen

On 06/10/2021 09:43, James Clark wrote:

+ Andi

> 
> 
> On 05/10/2021 11:10, John Garry wrote:
>> On 04/10/2021 17:00, Andrew Kilroy wrote:
>>> There are some syntactical mistakes in the json files for the Cortex A76
>>> N1 (Neoverse N1).  This was obstructing parsing from an external tool.
>>
>> If the trailing comma is not allowed by standard, then maybe we should fix our parsing tool to not allow it also. However maybe there is a good reason why we allow it..
> 
> It would be nice to do, because I have also made similar fixes before. We looked at the STRICT option
> in the parser (https://github.com/zserge/jsmn), but even then it seems to allow trailing commas.
> 
> Trailing commas are not allowed in the json standard, but there is a split between parsers
> where some allow it and others don't. Specifically the Python parser doesn't allow it, and Python
> can easily be involved in some workflow that parses these files.
> 
> The only way forwards I can think of is either getting a change accepted upstream to the parser
> and then updating it in perf, switching to a different parser, or doing some hack to add an extra
> step in perf to look for commas. None of which sound ideal.
> 

Looking at the license in jsmn.c, we seem to be ok to modify it (to 
error on non-standard trailing ',') - that parser has already apparently 
been modified in mainline.

If we do that then I hope that there are not to many violations in out 
JSONs, including downstream.

Thanks,
John

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json
  2021-10-06 16:26     ` John Garry
@ 2021-10-08  0:03       ` Andi Kleen
  2021-10-08  2:59         ` Ian Rogers
  0 siblings, 1 reply; 15+ messages in thread
From: Andi Kleen @ 2021-10-08  0:03 UTC (permalink / raw)
  To: John Garry, James Clark, Andrew Kilroy, linux-kernel,
	linux-perf-users, acme
  Cc: Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
	Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel


On 10/6/2021 9:26 AM, John Garry wrote:
> On 06/10/2021 09:43, James Clark wrote:
>
> + Andi
>
>>
>>
>> On 05/10/2021 11:10, John Garry wrote:
>>> On 04/10/2021 17:00, Andrew Kilroy wrote:
>>>> There are some syntactical mistakes in the json files for the 
>>>> Cortex A76
>>>> N1 (Neoverse N1).  This was obstructing parsing from an external tool.
>>>
>>> If the trailing comma is not allowed by standard, then maybe we 
>>> should fix our parsing tool to not allow it also. However maybe 
>>> there is a good reason why we allow it..
>>
>> It would be nice to do, because I have also made similar fixes 
>> before. We looked at the STRICT option
>> in the parser (https://github.com/zserge/jsmn), but even then it 
>> seems to allow trailing commas.
>>
>> Trailing commas are not allowed in the json standard, but there is a 
>> split between parsers
>> where some allow it and others don't. Specifically the Python parser 
>> doesn't allow it, and Python
>> can easily be involved in some workflow that parses these files.
>>
>> The only way forwards I can think of is either getting a change 
>> accepted upstream to the parser
>> and then updating it in perf, switching to a different parser, or 
>> doing some hack to add an extra
>> step in perf to look for commas. None of which sound ideal.
>>
>
> Looking at the license in jsmn.c, we seem to be ok to modify it (to 
> error on non-standard trailing ',') - that parser has already 
> apparently been modified in mainline.
>
> If we do that then I hope that there are not to many violations in out 
> JSONs, including downstream.


Sure we can modify the file. I already did some minor changes when I 
submitted it originally.

-Andi



^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json
  2021-10-08  0:03       ` Andi Kleen
@ 2021-10-08  2:59         ` Ian Rogers
  2021-10-08 10:34           ` James Clark
  0 siblings, 1 reply; 15+ messages in thread
From: Ian Rogers @ 2021-10-08  2:59 UTC (permalink / raw)
  To: Andi Kleen
  Cc: John Garry, James Clark, Andrew Kilroy, linux-kernel,
	linux-perf-users, acme, Will Deacon, Mathieu Poirier, Leo Yan,
	Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
	linux-arm-kernel

On Thu, Oct 7, 2021 at 5:03 PM Andi Kleen <ak@linux.intel.com> wrote:
>
>
> On 10/6/2021 9:26 AM, John Garry wrote:
> > On 06/10/2021 09:43, James Clark wrote:
> >
> > + Andi
> >
> >>
> >>
> >> On 05/10/2021 11:10, John Garry wrote:
> >>> On 04/10/2021 17:00, Andrew Kilroy wrote:
> >>>> There are some syntactical mistakes in the json files for the
> >>>> Cortex A76
> >>>> N1 (Neoverse N1).  This was obstructing parsing from an external tool.
> >>>
> >>> If the trailing comma is not allowed by standard, then maybe we
> >>> should fix our parsing tool to not allow it also. However maybe
> >>> there is a good reason why we allow it..
> >>
> >> It would be nice to do, because I have also made similar fixes
> >> before. We looked at the STRICT option
> >> in the parser (https://github.com/zserge/jsmn), but even then it
> >> seems to allow trailing commas.
> >>
> >> Trailing commas are not allowed in the json standard, but there is a
> >> split between parsers
> >> where some allow it and others don't. Specifically the Python parser
> >> doesn't allow it, and Python
> >> can easily be involved in some workflow that parses these files.
> >>
> >> The only way forwards I can think of is either getting a change
> >> accepted upstream to the parser
> >> and then updating it in perf, switching to a different parser, or
> >> doing some hack to add an extra
> >> step in perf to look for commas. None of which sound ideal.
> >>
> >
> > Looking at the license in jsmn.c, we seem to be ok to modify it (to
> > error on non-standard trailing ',') - that parser has already
> > apparently been modified in mainline.
> >
> > If we do that then I hope that there are not to many violations in out
> > JSONs, including downstream.
>
>
> Sure we can modify the file. I already did some minor changes when I
> submitted it originally.
>
> -Andi

jsmn is a somewhat frustrating way to work on json code and working on
a forked version of jsmn was frustrating in [1]. Could we assume
python on build systems and rewrite jevents in python?

Thanks,
Ian

[1] https://lore.kernel.org/lkml/20201110100346.2527031-1-irogers@google.com/

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json
  2021-10-08  2:59         ` Ian Rogers
@ 2021-10-08 10:34           ` James Clark
  0 siblings, 0 replies; 15+ messages in thread
From: James Clark @ 2021-10-08 10:34 UTC (permalink / raw)
  To: Ian Rogers, Andi Kleen
  Cc: John Garry, Andrew Kilroy, linux-kernel, linux-perf-users, acme,
	Will Deacon, Mathieu Poirier, Leo Yan, Mark Rutland,
	Alexander Shishkin, Jiri Olsa, Namhyung Kim, linux-arm-kernel



On 08/10/2021 03:59, Ian Rogers wrote:
> On Thu, Oct 7, 2021 at 5:03 PM Andi Kleen <ak@linux.intel.com> wrote:
>>
>>
>> On 10/6/2021 9:26 AM, John Garry wrote:
>>> On 06/10/2021 09:43, James Clark wrote:
>>>
>>> + Andi
>>>
>>>>
>>>>
>>>> On 05/10/2021 11:10, John Garry wrote:
>>>>> On 04/10/2021 17:00, Andrew Kilroy wrote:
>>>>>> There are some syntactical mistakes in the json files for the
>>>>>> Cortex A76
>>>>>> N1 (Neoverse N1).  This was obstructing parsing from an external tool.
>>>>>
>>>>> If the trailing comma is not allowed by standard, then maybe we
>>>>> should fix our parsing tool to not allow it also. However maybe
>>>>> there is a good reason why we allow it..
>>>>
>>>> It would be nice to do, because I have also made similar fixes
>>>> before. We looked at the STRICT option
>>>> in the parser (https://github.com/zserge/jsmn), but even then it
>>>> seems to allow trailing commas.
>>>>
>>>> Trailing commas are not allowed in the json standard, but there is a
>>>> split between parsers
>>>> where some allow it and others don't. Specifically the Python parser
>>>> doesn't allow it, and Python
>>>> can easily be involved in some workflow that parses these files.
>>>>
>>>> The only way forwards I can think of is either getting a change
>>>> accepted upstream to the parser
>>>> and then updating it in perf, switching to a different parser, or
>>>> doing some hack to add an extra
>>>> step in perf to look for commas. None of which sound ideal.
>>>>
>>>
>>> Looking at the license in jsmn.c, we seem to be ok to modify it (to
>>> error on non-standard trailing ',') - that parser has already
>>> apparently been modified in mainline.
>>>
>>> If we do that then I hope that there are not to many violations in out
>>> JSONs, including downstream.
>>
>>
>> Sure we can modify the file. I already did some minor changes when I
>> submitted it originally.
>>
>> -Andi
> 
> jsmn is a somewhat frustrating way to work on json code and working on
> a forked version of jsmn was frustrating in [1]. Could we assume
> python on build systems and rewrite jevents in python?

Seems reasonable to me, although maybe a big job. I suppose there could be
an empty generated pmu file for systems that don't have Python and only the
ones listed in pmu-events/arch/ would need it.

James
> 
> Thanks,
> Ian
> 
> [1] https://lore.kernel.org/lkml/20201110100346.2527031-1-irogers@google.com/
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2021-10-08 10:34 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-04 16:00 [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json Andrew Kilroy
2021-10-04 16:00 ` [PATCH 2/4] perf vendor events: Add new armv8 pmu events Andrew Kilroy
2021-10-05 10:01   ` John Garry
2021-10-04 16:00 ` [PATCH 3/4] perf vendor events: Categorise the Neoverse V1 counters Andrew Kilroy
2021-10-04 16:00 ` [PATCH 4/4] perf vendor events: Add the Neoverse V1 to arm64 mapfile Andrew Kilroy
2021-10-05  9:33   ` John Garry
2021-10-05 17:58     ` Arnaldo Carvalho de Melo
2021-10-06  8:20       ` Andrew Kilroy
2021-10-06  8:29         ` Andrew Kilroy
2021-10-05 10:10 ` [PATCH 1/4] perf vendor events: Syntax corrections in Neoverse N1 json John Garry
2021-10-06  8:43   ` James Clark
2021-10-06 16:26     ` John Garry
2021-10-08  0:03       ` Andi Kleen
2021-10-08  2:59         ` Ian Rogers
2021-10-08 10:34           ` James Clark

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