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From: Paolo Bonzini <pbonzini@redhat.com>
To: Sean Christopherson <seanjc@google.com>, Wei Huang <wei.huang2@amd.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
vkuznets@redhat.com, wanpengli@tencent.com, jmattson@google.com,
joro@8bytes.org, tglx@linutronix.de, mingo@redhat.com,
bp@alien8.de, x86@kernel.org, hpa@zytor.com
Subject: Re: [PATCH v3 3/3] KVM: SVM: Add 5-level page table support for SVM
Date: Thu, 19 Aug 2021 18:38:57 +0200 [thread overview]
Message-ID: <d5894435-c5e1-890d-880c-6b6390fe50d8@redhat.com> (raw)
In-Reply-To: <YR1EPNRNtIZZ7LXd@google.com>
On 18/08/21 19:32, Sean Christopherson wrote:
> On Wed, Aug 18, 2021, Wei Huang wrote:
>> When the 5-level page table is enabled on host OS, the nested page table
>> for guest VMs must use 5-level as well. Update get_npt_level() function
>> to reflect this requirement. In the meanwhile, remove the code that
>> prevents kvm-amd driver from being loaded when 5-level page table is
>> detected.
>>
>> Signed-off-by: Wei Huang <wei.huang2@amd.com>
>> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>
> If this patch authored by Paolo, he needs to be attributed via From:. If Paolo
> is a co-author, he needs a Co-developed-by:. If either of those is true, your
> SOB needs to be last in the chain since you are the last handler of the patch.
> If neither is true, Paolo's SOB should be removed.
I didn't even remember writing this, but it's possible I pseudocoded in
an email just like you did below.
>> - return PT64_ROOT_4LEVEL;
>> + bool la57 = (cr4_read_shadow() & X86_CR4_LA57) != 0;
>> +
>> + return la57 ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
>
> Why obfuscate this? KVM is completely hosed if pgtable_l5_enabled() doesn't
> match host CR4. E.g.
>
> return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
That also suggests the above pseudocoding scenario, where I'd be too
lazy to look up the correct spelling of pgtable_l5_enabled().
Paolo
>> #else
>> return PT32E_ROOT_LEVEL;
>> #endif
>> @@ -462,11 +464,6 @@ static int has_svm(void)
>> return 0;
>> }
>>
>> - if (pgtable_l5_enabled()) {
>> - pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n");
>> - return 0;
>> - }
>> -
>> return 1;
>> }
>>
>> --
>> 2.31.1
>>
>
next prev parent reply other threads:[~2021-08-19 16:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-18 16:55 [PATCH v3 0/3] SVM 5-level page table support Wei Huang
2021-08-18 16:55 ` [PATCH v3 1/3] KVM: x86: Allow CPU to force vendor-specific TDP level Wei Huang
2021-08-18 16:55 ` [PATCH v3 2/3] KVM: x86: Handle the case of 5-level shadow page table Wei Huang
2021-08-18 17:15 ` Sean Christopherson
2021-08-19 16:36 ` Paolo Bonzini
2021-08-18 18:00 ` Tom Lendacky
2021-08-18 16:55 ` [PATCH v3 3/3] KVM: SVM: Add 5-level page table support for SVM Wei Huang
2021-08-18 17:32 ` Sean Christopherson
2021-08-19 16:38 ` Paolo Bonzini [this message]
2021-08-19 16:43 ` [PATCH v3 0/3] SVM 5-level page table support Paolo Bonzini
2021-08-23 9:20 ` Maxim Levitsky
2021-08-23 15:15 ` Wei Huang
2021-08-23 16:10 ` Sean Christopherson
2021-08-23 18:10 ` Maxim Levitsky
2021-08-23 18:06 ` Maxim Levitsky
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