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From: Greentime Hu <green.hu@gmail.com>
To: linux-kernel@vger.kernel.org, arnd@arndb.de,
	greentime@andestech.com, green.hu@gmail.com
Subject: [PATCH 2/3] nds32: To refine readability of INT_MASK_INITAIAL_VAL
Date: Mon, 30 Apr 2018 15:20:40 +0800	[thread overview]
Message-ID: <ec252c56d4e56b769a57e4a91ddd9dfdd440d641.1525072600.git.greentime@andestech.com> (raw)
In-Reply-To: <a42871ba8088e343cdfd405426ea25e5727116af.1525072600.git.greentime@andestech.com>
In-Reply-To: <a42871ba8088e343cdfd405426ea25e5727116af.1525072600.git.greentime@andestech.com>

Refine readability of INT_MASK_INITAIAL_VAL with meaningful macro instead
of magic number.

Signed-off-by: Greentime Hu <greentime@andestech.com>
---
 arch/nds32/include/asm/bitfield.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/nds32/include/asm/bitfield.h b/arch/nds32/include/asm/bitfield.h
index c73f71d67744..28b7d797fd59 100644
--- a/arch/nds32/include/asm/bitfield.h
+++ b/arch/nds32/include/asm/bitfield.h
@@ -336,7 +336,7 @@
 #define INT_MASK_mskIDIVZE	( 0x1  << INT_MASK_offIDIVZE )
 #define INT_MASK_mskDSSIM	( 0x1  << INT_MASK_offDSSIM )
 
-#define INT_MASK_INITAIAL_VAL	0x10003
+#define INT_MASK_INITAIAL_VAL	(INT_MASK_mskDSSIM|INT_MASK_mskIDIVZE)
 
 /******************************************************************************
  * ir15: INT_PEND (Interrupt Pending Register)
-- 
1.9.5

  reply	other threads:[~2018-04-30  7:22 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-30  7:20 [PATCH 1/3] nds32: Fix the virtual address may map too much range by tlbop issue Greentime Hu
2018-04-30  7:20 ` Greentime Hu [this message]
2018-04-30  7:20 ` [PATCH 3/3] nds32: To fix a cache inconsistency issue by setting correct cacheability of NTC Greentime Hu

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