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[92.145.152.65]) by smtp.gmail.com with ESMTPSA id bk24sm2421518pjb.26.2021.08.10.03.07.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Aug 2021 03:07:18 -0700 (PDT) Subject: Re: [PATCH 1/3] PCI: brcmstb: Break register definitions into separate header To: Jeremy Linton , linux-pci@vger.kernel.org Cc: lorenzo.pieralisi@arm.com, nsaenz@kernel.org, bhelgaas@google.com, rjw@rjwysocki.net, lenb@kernel.org, robh@kernel.org, kw@linux.com, f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20210805211200.491275-1-jeremy.linton@arm.com> <20210805211200.491275-2-jeremy.linton@arm.com> From: Florian Fainelli Message-ID: Date: Tue, 10 Aug 2021 03:07:13 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.12.0 MIME-Version: 1.0 In-Reply-To: <20210805211200.491275-2-jeremy.linton@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/5/2021 2:11 PM, Jeremy Linton wrote: > We are about to create a standalone ACPI quirk module for the > bcmstb controller. Lets move the register definitions into a separate > file so they can be shared between the APCI quirk and the normal > host bridge driver. > > Signed-off-by: Jeremy Linton > --- > drivers/pci/controller/pcie-brcmstb.c | 179 +------------------------ > drivers/pci/controller/pcie-brcmstb.h | 182 ++++++++++++++++++++++++++ > 2 files changed, 183 insertions(+), 178 deletions(-) > create mode 100644 drivers/pci/controller/pcie-brcmstb.h You moved more than just register definitions into pcie-brcmstb.h you also moved internal structure definitions, enumerations, etc. which are not required since pcie-brcmstb-acpi.c does not access the brcm_pcie structure but open codes accesses to the MISC_STATUS register instead. There are no include guards added to this file (it is debatable whether we should add them), and it is also not covered by the existing BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE MAINTAINERS file entry. Given that there can be new platforms supported by this PCIe controller in the future possibly with the same limitations as the 2711, but with a seemingly different MISC_STATUS layout, you will have to think about a solution that scales, maybe we cross that bridge when we get there. -- Florian