From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21A21C432BE for ; Thu, 5 Aug 2021 07:35:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 039CD60720 for ; Thu, 5 Aug 2021 07:35:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231905AbhHEHgI (ORCPT ); Thu, 5 Aug 2021 03:36:08 -0400 Received: from smtp-relay-canonical-0.canonical.com ([185.125.188.120]:43934 "EHLO smtp-relay-canonical-0.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230523AbhHEHfc (ORCPT ); Thu, 5 Aug 2021 03:35:32 -0400 Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-canonical-0.canonical.com (Postfix) with ESMTPS id AA3513F352 for ; Thu, 5 Aug 2021 07:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1628148917; bh=kMB7D3FwR8aaeZ7GkcRhY+XNtv5mwLtm+gleHTDDxFM=; h=Subject:To:Cc:References:From:Message-ID:Date:MIME-Version: In-Reply-To:Content-Type; b=Lv4wV3HekGroQ/hTPtJtVipPEPt9mDzSD4Goe7wyZHqIjS3ZjasPftbluaQWapHOz uy8WLKfkEgujQSC1/ir4A7lJoVpMaDl8y/AU2s+DOza/vmN1ad4/XjOiePXL1eQLBv NxFJ+xx3vnkfO0cEgV31Ah6f9+tA8/oG3uW63+tfmFK4ZuMXVD4M4VuZADGjJTZVCe 8/StMN2gJdOvFFmeMwAn3j3gX6aIITA40xKYc37a0XuBP7IgEa5KI6v+ZaoFwn27Xj TOpPS44HjkkmaA2Np9U3t+h5VX1kcF7xD0YFI7e4J//iVsWq14UjWFJh5/v1gxnsOu 0OT3jUQSlElMg== Received: by mail-ed1-f71.google.com with SMTP id c1-20020aa7df010000b02903bb5c6f746eso2701974edy.10 for ; Thu, 05 Aug 2021 00:35:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=kMB7D3FwR8aaeZ7GkcRhY+XNtv5mwLtm+gleHTDDxFM=; b=iXYUGv6qLgDRyqw2oyfMIXtPUvZrmSZsaKo9h+FhzVSnNxPSQU0JEDPaFmN58bETj+ 7zvEGYZXBqksXT75yz13tCBbJrR/cDX4mvgSAaxwy6Vt9rsLiZLzs2/Rym0hfmbGdEhp WeOmTt64fmkMhfS9v+VNwAS11amwYWi2uGf+3Uj8ZlchcaSFPhlq3qLgxRlpr9PBXJ5B bdkCLBnE4Bur6Q69+F8pw5ia+NyIXe4zcECl2lsY9/V/+f4QYffUOYbVHNtz+jI0dgGs I1vtbo3cDTAM5aB70N/l76ID0N36e7Jx2C1kFEIYIwM//Lm1spX9H+qbykIZA/l0SZ// EDVA== X-Gm-Message-State: AOAM530Lt9jMvFUMkR9GtboIcie6GEgBjAdvpMar+dEpD1YrdifoUWsB m+lriBOuZOZRmfqYi9Odc6N91xdoWVeG6ijcRpJCN72JRSqf6ANlvNO4kp58oks8ciMzSuC5eAR 77NHa62NKw/0wdwg3BwjMV737fAqiynMu/JMEDnqeIg== X-Received: by 2002:a17:906:a0a:: with SMTP id w10mr3499020ejf.416.1628148915213; Thu, 05 Aug 2021 00:35:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyPcQUWoeFo8Oc3RFUk7sBrXe1NGu+OxbWafCL6RAdlu//8RMlDAyb13M9QoYaDGHWGqoadKg== X-Received: by 2002:a17:906:a0a:: with SMTP id w10mr3499000ejf.416.1628148915094; Thu, 05 Aug 2021 00:35:15 -0700 (PDT) Received: from [192.168.8.102] ([86.32.42.198]) by smtp.gmail.com with ESMTPSA id r16sm1886421edt.15.2021.08.05.00.35.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Aug 2021 00:35:14 -0700 (PDT) Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support To: Marc Zyngier Cc: Sam Protsenko , Sylwester Nawrocki , Chanwoo Choi , Linus Walleij , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" References: <20210730144922.29111-1-semen.protsenko@linaro.org> <20210730144922.29111-13-semen.protsenko@linaro.org> <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> <87zgtwbb6x.wl-maz@kernel.org> From: Krzysztof Kozlowski Message-ID: Date: Thu, 5 Aug 2021 09:35:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <87zgtwbb6x.wl-maz@kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/08/2021 09:30, Marc Zyngier wrote: > On Thu, 05 Aug 2021 08:17:14 +0100, > Krzysztof Kozlowski wrote: >> >> On 04/08/2021 23:30, Sam Protsenko wrote: >>>>> >>>>> Nice catch! Actually there is an error (typo?) in SoC's TRM, saying >>>>> that Virtual Interface Control Register starts at 0x3000 offset (from >>>>> 0x12a00000), where it obviously should be 0x4000, that's probably >>>>> where this dts error originates from. Btw, I'm also seeing the same >>>>> error in exynos7.dtsi. >>>> >>>> What's the error exactly? The "Virtual interface control register" >>>> offset (3rd region) is set properly to 0x4000 on Exynos7. Also one for >>>> the Exynos5433 looks correct. >>>> >>> >>> The issue is that 2nd region's size is 0x1000, but it must be 0x2000. >>> It's defined by GIC-400 architecture, as I understand. Please look at >>> [1], table 3-1 has very specific offsets and sizes for each functional >>> block, and each particular SoC must adhere to that spec. So having >>> 0x1000 for 2nd region can't be correct. And because exynos7.dtsi has >>> GIC-400 as well, and 0x1000 is specified there for 2nd region size >>> too, so I presume there is the same mistake there. >> >> I understand, the range length has indeed same mistake. However it does >> not matter that much There are no registers pass 0x10C (so pass 0x1000). >> This address space is not used. > > I have no idea which spec you are looking at, but the GICv2 > architecture (of which GIC400 is an implementation) definitely has a > register in the second 4kB page of the CPU interface. It contains the > GICC_DIR register, which is used to deactivate an interrupt when > EOIMode==1. > > Linux actively uses it when started at EL2. I was checking Exynos TRM and it seems it has one more bug... The ARM datasheet [1] indeed mentions GICC_DIR at 0x1000. I'll add "Fixes" tag to my fix for Exynos7. https://developer.arm.com/documentation/ddi0471/b/programmers-model/cpu-interface-register-summary Best regards, Krzysztof