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From: Xiaoyao Li <xiaoyao.li@intel.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/5] KVM: VMX: Use cached vmx->pt_desc.addr_range
Date: Tue, 24 Aug 2021 23:42:44 +0800 [thread overview]
Message-ID: <faf53e42-428b-5d54-0a29-2dbe3af6ddd2@intel.com> (raw)
In-Reply-To: <YSUPKmtP6Dcl1yio@google.com>
On 8/24/2021 11:24 PM, Sean Christopherson wrote:
> On Tue, Aug 24, 2021, Xiaoyao Li wrote:
>> The number of guest's valid PT ADDR MSRs is cached in
>
> Can you do s/cached/precomputed in the shortlog and changelog? Explanation below.
OK.
>> vmx->pt_desc.addr_range. Use it instead of calculating it again.
>>
>> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
>> ---
>> arch/x86/kvm/vmx/vmx.c | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
>> index e0a9460e4dab..7ed96c460661 100644
>> --- a/arch/x86/kvm/vmx/vmx.c
>> +++ b/arch/x86/kvm/vmx/vmx.c
>> @@ -2202,8 +2202,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>> if (!pt_can_write_msr(vmx))
>> return 1;
>> index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
>> - if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
>> - PT_CAP_num_address_ranges))
>> + if (index >= 2 * vmx->pt_desc.addr_range)
>
> Ugh, "validate" is a lie, a better name would be intel_pt_get_cap() or so. There
> is no validation, the helper is simply extracting the requested cap from the
> passed in array of capabilities.
>
> That matters in this case because the number of address ranges exposed to the
> guest is not bounded by the number of address ranges present in hardware, i.e.
> it's not "validated". And that matters because KVM uses vmx->pt_desc.addr_range
> to pass through the ADDRn_{A,B} MSRs when tracing enabled. In other words,
> userspace can expose MSRs to the guest that do not exist.
That's why I provided patch 5.
> The bug shouldn't be a security issue, so long as Intel CPUs are bug free and
> aren't doing silly things with MSR indexes. The number of possible address ranges
> is encoded in three bits, thus the theoretical max is 8 ranges. So userspace can't
> get access to arbitrary MSRs, just ADDR0_A -> ADDR7_B.
>
> And since KVM would be modifying the "validated" value, it's more than just a
> cache, hence the request to use "precomputed".
>
> Finally, vmx_get_msr() should use the precomputed value as well.
Argh, I missed it.
> P.S. If you want to introduce a bit of churn, s/addr_range/nr_addr_ranges would
> be a welcome change as well.
In a separate patch?
>> return 1;
>> if (is_noncanonical_address(data, vcpu))
>> return 1;
>> --
>> 2.27.0
>>
next prev parent reply other threads:[~2021-08-24 15:43 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-24 11:07 [PATCH 0/5] KVM: VMX: PT (processor trace) optimizations and fixes Xiaoyao Li
2021-08-24 11:07 ` [PATCH 1/5] KVM: VMX: Restore host's MSR_IA32_RTIT_CTL when it's not zero Xiaoyao Li
2021-08-24 17:54 ` Sean Christopherson
2021-08-24 11:07 ` [PATCH 2/5] KVM: VMX: Use cached vmx->pt_desc.addr_range Xiaoyao Li
2021-08-24 15:24 ` Sean Christopherson
2021-08-24 15:42 ` Xiaoyao Li [this message]
2021-08-24 11:07 ` [PATCH 3/5] KVM: VMX: RTIT_CTL_BRANCH_EN has no dependency on other CPUID bit Xiaoyao Li
2021-08-25 3:30 ` Like Xu
2021-08-25 4:19 ` Xiaoyao Li
2021-08-25 6:08 ` Like Xu
2021-08-25 6:33 ` Xiaoyao Li
2021-08-25 8:14 ` Like Xu
2021-08-25 8:58 ` Xiaoyao Li
2021-08-25 11:53 ` Alexander Shishkin
2021-08-24 11:07 ` [PATCH 4/5] KVM: VMX: Disallow PT MSRs accessing if PT is not exposed to guest Xiaoyao Li
2021-08-24 14:20 ` Sean Christopherson
2021-08-24 15:35 ` Xiaoyao Li
2021-08-24 16:48 ` Sean Christopherson
2021-08-24 11:07 ` [PATCH 5/5] KVM: VMX: Check Intel PT related CPUID leaves Xiaoyao Li
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