From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 762B5C433FE for ; Thu, 14 Oct 2021 11:37:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5AE0C6101A for ; Thu, 14 Oct 2021 11:37:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231168AbhJNLj5 convert rfc822-to-8bit (ORCPT ); Thu, 14 Oct 2021 07:39:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230499AbhJNLjz (ORCPT ); Thu, 14 Oct 2021 07:39:55 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88E65C06174E for ; Thu, 14 Oct 2021 04:37:50 -0700 (PDT) Received: from lupine.hi.pengutronix.de ([2001:67c:670:100:3ad5:47ff:feaf:1a17] helo=lupine) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1maz3Q-0005y5-2b; Thu, 14 Oct 2021 13:37:44 +0200 Received: from pza by lupine with local (Exim 4.92) (envelope-from ) id 1maz3M-000463-0H; Thu, 14 Oct 2021 13:37:40 +0200 Message-ID: Subject: Re: [PATCH v2 2/3] phy/rockchip: add naneng combo phy for RK3568 From: Philipp Zabel To: Yifeng Zhao , heiko@sntech.de, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, vkoul@kernel.org, michael.riesch@wolfvision.net, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, kishon@ti.com Date: Thu, 14 Oct 2021 13:37:39 +0200 In-Reply-To: <20211013101938.28061-3-yifeng.zhao@rock-chips.com> References: <20211013101938.28061-1-yifeng.zhao@rock-chips.com> <20211013101938.28061-3-yifeng.zhao@rock-chips.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT User-Agent: Evolution 3.30.5-1.1 MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:3ad5:47ff:feaf:1a17 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Yifeng, On Wed, 2021-10-13 at 18:19 +0800, Yifeng Zhao wrote: > This patch implements a combo phy driver for Rockchip SoCs > with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy, > sata-phy or sgmii-phy. > > Signed-off-by: Yifeng Zhao > --- > > Changes in v2: > - Using api devm_platform_get_and_ioremap_resource. > - Modify rockchip_combphy_set_Mode. > - Add some PHY registers definition. > > drivers/phy/rockchip/Kconfig | 8 + > drivers/phy/rockchip/Makefile | 1 + > .../rockchip/phy-rockchip-naneng-combphy.c | 650 ++++++++++++++++++ > 3 files changed, 659 insertions(+) > create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > [...] > diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > new file mode 100644 > index 000000000000..fbfc5fbbd5b8 > --- /dev/null > +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > @@ -0,0 +1,650 @@ [...] > +static int rockchip_combphy_parse_dt(struct device *dev, > + struct rockchip_combphy_priv *priv) > +{ > + const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; > + int ret, mac_id; > + [...] > + priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb"); Please use devm_reset_control_get_optional_exclusive(). Also, apb_rst is never used? > + if (IS_ERR(priv->apb_rst)) { > + ret = PTR_ERR(priv->apb_rst); > + > + if (ret != -EPROBE_DEFER) > + dev_warn(dev, "failed to get apb reset\n"); > + > + return ret; Any reason not to use dev_err_probe()? > + } > + > + priv->phy_rst = devm_reset_control_get_optional(dev, "combphy"); Please use devm_reset_control_get_optional_exclusive(). > + if (IS_ERR(priv->phy_rst)) { > + ret = PTR_ERR(priv->phy_rst); > + > + if (ret != -EPROBE_DEFER) > + dev_warn(dev, "failed to get phy reset\n"); > + > + return ret; Same as above. > + } > + > + return reset_control_assert(priv->phy_rst); It is unexpected that a function called rockchip_combphy_parse_dt() already changes device state. I'd move the reset_control_assert() out into rockchip_combphy_probe(). regards Philipp