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From: ebiederm@xmission.com (Eric W. Biederman)
To: Zwane Mwaikambo <zwane@infradead.org>
Cc: Ashok Raj <ashok.raj@intel.com>, Ingo Molnar <mingo@elte.hu>,
Andrew Morton <akpm@osdl.org>,
linux-kernel@vger.kernel.org, "Lu, Yinghai" <yinghai.lu@amd.com>,
Natalie Protasevich <protasnb@gmail.com>, Andi Kleen <ak@suse.de>,
Coywolf Qi Hunt <coywolf@lovecn.org>
Subject: Re: What are the real ioapic rte programming constraints?
Date: Sun, 11 Feb 2007 03:20:18 -0700 [thread overview]
Message-ID: <m13b5d0zdp.fsf@ebiederm.dsl.xmission.com> (raw)
In-Reply-To: <Pine.LNX.4.64.0702102146380.8245@montezuma.fsmlabs.com> (Zwane Mwaikambo's message of "Sat, 10 Feb 2007 21:57:56 -0800 (PST)")
Zwane Mwaikambo <zwane@infradead.org> writes:
> On Sat, 10 Feb 2007, Eric W. Biederman wrote:
>
>> There are not enough details in the justification to really understand
>> the issue so I'm asking to see if someone has some more details.
>>
>> The description makes the assertion that reprograming the ioapic
>> when an interrupt is pending is the only safe way to handle this.
>> Since edge triggered interrupts cannot be pending at the ioapic I know
>> it is not talking level triggered interrupts.
>>
>> However it is not possible to fully reprogram a level triggered
>> interrupt when the interrupt is pending as the ioapic will not
>> receive the interrupt acknowledgement. So it turns out I have
>> broken this change for several kernel releases without people
>> screaming at me about io_apic problems.
>>
>> Currently I am disabling the irq on the ioapic before reprogramming
>> it so I do not run into issues. Does that solve the concerns that
>> were patched around by only reprogramming interrupt redirection
>> table entry in interrupt handlers?
>
> Hi Eric,
> Could you outline in pseudocode where you're issuing the mask? If
> it's done whilst an irq is pending some (intel 7500 based) chipsets will
> not actually mask it but treat it as a 'legacy' IRQ and deliver it
> anyway. Using the masked whilst pending logic avoids all of that.
The code currently in the kernel does:
pending
mask
read io_apic
ack
reprogram vector and destination
unmask
So I guess it does retain the bug fix.
What I am looking at doing is:
mask
read io_apic
-- Past this point no more irqs are expected from the io_apic
-- Now I work to drain any inflight/pending instances of the irq
send ipi to all irq destinations cpus and wait for it to return
read lapic
disable local irqs
take irq lock
-- Now no more irqs are expected to arrive
reprogram vector and destination
enable local irqs
unmask
What I need to ensure is that I have a point where I will not receive any
new messages from an ioapic about a particular irq anymore. Even if
everything is working perfectly setting the disable bit is not enough
because there could be an irq message in flight. So I need to give any
in flight irqs a chance to complete.
With a little luck that logic will cover your 7500 disable race as
well. If not and there is a reasonable work around we should look at
that. This is not a speed critical path so we can afford to do a
little more work.
The version of this that I am currently testing is below.
Eric
/*
* Synchronize the local APIC and the CPU by doing
* a dummy read from the local APIC
*/
static inline void lapic_sync(void)
{
apic_read(APIC_ID);
}
static void affinity_noop(void *info)
{
return;
}
static void mask_get_irq(unsigned int irq)
{
struct irq_desc *desc = irq_desc + irq;
int cpu;
spin_lock(&vector_lock);
/*
* Mask the irq so it will no longer occur
*/
desc->chip->mask(irq);
/* If I can run a lower priority vector on another cpu
* then obviously the irq has completed on that cpu. SMP call
* function is lower priority then all of the hardware
* irqs.
*/
for_each_cpu_mask(cpu, desc->affinity)
smp_call_function_single(cpu, affinity_noop, NULL, 0, 1);
/*
* Ensure irqs have cleared the local cpu
*/
lapic_sync();
local_irq_disable();
lapic_sync();
spin_lock(&desc->lock);
}
static void unmask_put_irq(unsigned int irq)
{
struct irq_desc *desc = irq_desc + irq;
spin_unlock(&desc->lock);
local_irq_enable();
desc->chip->unmask(irq);
spin_unlock(&vector_lock);
}
static void set_ioapic_affinity_level_irq(unsigned int irq, cpumask_t mask)
{
unsigned int dest;
int vector;
/*
* Ensure all of the irq handlers for this irq have completed.
* i.e. drain all pending irqs
*/
mask_get_irq(irq);
cpus_and(mask, mask, cpu_online_map);
if (cpus_empty(mask))
goto out;
vector = __assign_irq_vector(irq, mask, &mask);
if (vector < 0)
goto out;
dest = cpu_mask_to_apicid(mask);
/*
* Only the high 8 bits are valid
*/
dest = SET_APIC_LOGICAL_ID(dest);
spin_lock(&ioapic_lock);
__target_IO_APIC_irq(irq, dest, vector);
spin_unlock(&ioapic_lock);
set_native_irq_info(irq, mask);
out:
unmask_put_irq(irq);
}
next prev parent reply other threads:[~2007-02-11 10:23 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <200701221116.13154.luigi.genoni@pirelli.com>
2007-01-22 17:14 ` System crash after "No irq handler for vector" linux 2.6.19 Eric W. Biederman
[not found] ` <200701231051.32945.luigi.genoni@pirelli.com>
2007-01-23 12:18 ` Eric W. Biederman
[not found] ` <Pine.LNX.4.64.0701232052330.32111@baldios.it.pirelli.com>
2007-01-31 8:39 ` Eric W. Biederman
[not found] ` <200701311549.22512.luigi.genoni@pirelli.com>
2007-02-01 5:56 ` [PATCH] x86_64: Survive having no irq mapping for a vector Eric W. Biederman
2007-02-01 5:59 ` System crash after "No irq handler for vector" linux 2.6.19 Eric W. Biederman
2007-02-01 7:20 ` Eric W. Biederman
[not found] ` <200702021848.55921.luigi.genoni@pirelli.com>
2007-02-02 18:02 ` Eric W. Biederman
[not found] ` <200702021905.39922.luigi.genoni@pirelli.com>
2007-02-02 18:32 ` Eric W. Biederman
2007-02-03 0:31 ` [PATCH 1/2] x86_64 irq: Simplfy __assign_irq_vector Eric W. Biederman
2007-02-03 0:35 ` [PATCH 2/2] x86_64 irq: Handle irqs pending in IRR during irq migration Eric W. Biederman
2007-02-03 1:05 ` Andrew Morton
2007-02-03 1:39 ` Eric W. Biederman
2007-02-03 2:01 ` Andrew Morton
2007-02-03 7:32 ` Arjan van de Ven
2007-02-03 7:55 ` Eric W. Biederman
2007-02-03 14:31 ` l.genoni
2007-02-03 10:01 ` Andi Kleen
2007-02-03 10:22 ` Eric W. Biederman
2007-02-03 10:26 ` Andi Kleen
2007-02-06 7:36 ` Ingo Molnar
2007-02-06 8:57 ` Eric W. Biederman
[not found] ` <200702061012.25910.luigi.genoni@pirelli.com>
2007-02-06 22:05 ` Eric W. Biederman
2007-02-06 22:16 ` Eric W. Biederman
2007-02-06 22:25 ` Ingo Molnar
2007-02-07 2:33 ` Eric W. Biederman
2007-02-08 11:48 ` Eric W. Biederman
2007-02-08 20:19 ` Eric W. Biederman
2007-02-09 6:40 ` Eric W. Biederman
2007-02-10 23:52 ` What are the real ioapic rte programming constraints? Eric W. Biederman
2007-02-11 5:57 ` Zwane Mwaikambo
2007-02-11 10:20 ` Eric W. Biederman [this message]
2007-02-11 16:16 ` Zwane Mwaikambo
2007-02-11 22:01 ` Eric W. Biederman
2007-02-12 1:05 ` Zwane Mwaikambo
2007-02-12 4:51 ` Eric W. Biederman
2007-02-23 10:51 ` Conclusions from my investigation about ioapic programming Eric W. Biederman
2007-02-23 11:10 ` [PATCH 0/14] x86_64 irq related fixes and cleanups Eric W. Biederman
2007-02-23 11:11 ` [PATCH 01/14] x86_64 irq: Simplfy __assign_irq_vector Eric W. Biederman
2007-02-23 11:13 ` [PATCH 02/14] irq: Remove set_native_irq_info Eric W. Biederman
2007-02-23 11:15 ` [PATCH 03/14] x86_64 irq: Kill declaration of removed array, interrupt Eric W. Biederman
2007-02-23 11:16 ` [PATCH 04/14] x86_64 irq: Remove the unused vector parameter from ioapic_register_intr Eric W. Biederman
2007-02-23 11:19 ` [PATCH 05/14] x86_64 irq: Refactor setup_IO_APIC_irq Eric W. Biederman
2007-02-23 11:20 ` [PATCH 06/14] x86_64 irq: Simplfiy the set_affinity logic Eric W. Biederman
2007-02-23 11:23 ` [PATCH 07/14] x86_64 irq: In __DO_ACTION perform the FINAL action for every entry Eric W. Biederman
2007-02-23 11:26 ` [PATCH 08/14] x86_64 irq: Use NR_IRQS not NR_IRQ_VECTORS Eric W. Biederman
2007-02-23 11:32 ` [PATCH 09/14] x86_64 irq: Begin consolidating per_irq data in structures Eric W. Biederman
2007-02-23 11:35 ` [PATCH 10/14] x86_64 irq: Simplify assign_irq_vector's arguments Eric W. Biederman
2007-02-23 11:36 ` [PATCH 11/14] x86_64 irq: Remove unnecessary irq 0 setup Eric W. Biederman
2007-02-23 11:38 ` [PATCH 12/14] x86_64 irq: Add constants for the reserved IRQ vectors Eric W. Biederman
2007-02-23 11:40 ` [PATCH 13/14] x86_64 irq: Safely cleanup an irq after moving it Eric W. Biederman
2007-02-25 11:53 ` Mika Penttilä
2007-02-25 12:09 ` Eric W. Biederman
2007-02-23 11:46 ` [PATCH 14/14] genirq: Mask irqs when migrating them Eric W. Biederman
2007-02-23 12:01 ` [PATCH] x86_64 irq: Document what works and why on ioapics Eric W. Biederman
2007-02-24 2:06 ` [PATCH 14/14] genirq: Mask irqs when migrating them Siddha, Suresh B
2007-02-27 20:26 ` Andrew Morton
2007-02-27 20:41 ` Eric W. Biederman
2007-02-25 10:43 ` [PATCH 12/14] x86_64 irq: Add constants for the reserved IRQ vectors Pavel Machek
2007-02-25 11:15 ` Eric W. Biederman
2007-02-25 19:48 ` Pavel Machek
2007-02-25 21:01 ` Eric W. Biederman
2007-02-25 21:13 ` Pavel Machek
2007-02-23 16:48 ` Conclusions from my investigation about ioapic programming Jeff V. Merkey
2007-02-23 18:10 ` Eric W. Biederman
2007-02-23 17:48 ` Jeff V. Merkey
2007-02-24 4:05 ` Eric W. Biederman
2007-02-24 5:44 ` Jeffrey V. Merkey
2007-02-23 17:48 ` Jeff V. Merkey
[not found] ` <32209efe0702111212j77f5011xe2430cb13c13686@mail.gmail.com>
2007-02-11 21:36 ` What are the real ioapic rte programming constraints? Eric W. Biederman
2007-02-03 9:50 ` [PATCH 1/2] x86_64 irq: Simplfy __assign_irq_vector Andi Kleen
2007-02-03 0:40 ` System crash after "No irq handler for vector" linux 2.6.19 Eric W. Biederman
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