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From: tip-bot for David Wang <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: mingo@kernel.org, tglx@linutronix.de,
	linux-kernel@vger.kernel.org, davidwang@zhaoxin.com,
	hpa@zytor.com
Subject: [tip:x86/cpu] x86/Centaur: Report correct CPU/cache topology
Date: Sun, 13 May 2018 05:02:23 -0700	[thread overview]
Message-ID: <tip-5a19009043fcffd1591b04a588d53336a66855d5@git.kernel.org> (raw)
In-Reply-To: <1525314766-18910-4-git-send-email-davidwang@zhaoxin.com>

Commit-ID:  5a19009043fcffd1591b04a588d53336a66855d5
Gitweb:     https://git.kernel.org/tip/5a19009043fcffd1591b04a588d53336a66855d5
Author:     David Wang <davidwang@zhaoxin.com>
AuthorDate: Thu, 3 May 2018 10:32:46 +0800
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Sun, 13 May 2018 12:06:13 +0200

x86/Centaur: Report correct CPU/cache topology

Centaur CPUs enumerate the cache topology in the same way as Intel CPUs,
but the function is unused so for. The Centaur init code also misses to
initialize x86_info::max_cores, so the CPU topology can't be described
correctly.

Initialize x86_info::max_cores and invoke init_cacheinfo() to make
CPU and cache topology information available and correct.

Signed-off-by: David Wang <davidwang@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: lukelin@viacpu.com
Cc: qiyuanwang@zhaoxin.com
Cc: gregkh@linuxfoundation.org
Cc: brucechang@via-alliance.com
Cc: timguo@zhaoxin.com
Cc: cooperyan@zhaoxin.com
Cc: hpa@zytor.com
Cc: benjaminpan@viatech.com
Link: https://lkml.kernel.org/r/1525314766-18910-4-git-send-email-davidwang@zhaoxin.com

---
 arch/x86/kernel/cpu/centaur.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 80d5110481ec..c265494234e6 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -160,6 +160,11 @@ static void init_centaur(struct cpuinfo_x86 *c)
 	clear_cpu_cap(c, 0*32+31);
 #endif
 	early_init_centaur(c);
+	init_intel_cacheinfo(c);
+	c->x86_max_cores = detect_num_cpu_cores(c);
+#ifdef CONFIG_X86_32
+	detect_ht(c);
+#endif
 
 	if (c->cpuid_level > 9) {
 		unsigned int eax = cpuid_eax(10);

  reply	other threads:[~2018-05-13 12:02 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-03  2:32 [PATCH 0/3] x86/CPU: Report correct cpu/cache topo for Centaur CPUs and some minor changes David Wang
2018-05-03  2:32 ` [PATCH 1/3] x86/CPU: Replace intel_num_cpu_cores with detect_num_cpu_cores David Wang
2018-05-13 12:01   ` [tip:x86/cpu] x86/CPU: Make intel_num_cpu_cores() generic tip-bot for David Wang
2018-05-03  2:32 ` [PATCH 2/3] x86/cpu: Include cpu_detect_cache_sizes in init_intel_cacheinfo David Wang
2018-05-13 12:01   ` [tip:x86/cpu] x86/CPU: Move cpu_detect_cache_sizes() into init_intel_cacheinfo() tip-bot for David Wang
2018-05-13 14:18   ` tip-bot for David Wang
2018-05-03  2:32 ` [PATCH 3/3] x86/Centaur: Report correct CPU/cache topology David Wang
2018-05-13 12:02   ` tip-bot for David Wang [this message]
2018-05-13 14:19   ` [tip:x86/cpu] " tip-bot for David Wang

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