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From: Dario Alcocer <dalcocer@helixd.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: netdev@vger.kernel.org
Subject: Re: Marvell switch port shows LOWERLAYERDOWN, ping fails
Date: Wed, 28 Jul 2021 12:37:14 -0700 [thread overview]
Message-ID: <11b81662-e9ce-591c-122a-af280f1e1f59@helixd.com> (raw)
In-Reply-To: <YQGu2r02XdMR5Ajp@lunn.ch>
On 7/28/21 12:24 PM, Andrew Lunn wrote:
> On Wed, Jul 28, 2021 at 11:33:35AM -0700, Dario Alcocer wrote:
>> On 7/28/21 11:23 AM, Andrew Lunn wrote:
>>> On Wed, Jul 28, 2021 at 11:07:37AM -0700, Dario Alcocer wrote:
>>>> It appears the port link-state issue is caused by the mv88e6xxx switch
>>>> driver. The function mv88e6xxx_mac_config identifies the PHY as internal and
>>>> skips the call to mv88e6xxx_port_setup_mac.
>>>>
>>>> It does not make sense to me why internal PHY configuration should be
>>>> skipped.
>>>
>>> The switch should do the configuration itself for internal PHYs. At
>>> least that works for other switches. What value does CMODE have for
>>> the port? 0xf?
>>>
>>> Andrew
>>>
>>
>> Is CMODE available via the DSA debugfs? Here are the registers for port0,
>> which should be lan1:
>>
>> root@dali:~# ls /sys/kernel/debug/dsa/switch0/
>> port0/ port1/ port2/ port3/ port4/ port5/
>> port6/ tag_protocol tree
>> root@dali:~# ls /sys/kernel/debug/dsa/switch0/port0/
>> fdb mdb regs stats vlan
>> root@dali:~# cat /sys/kernel/debug/dsa/switch0/port0/regs
>> 0: 100f
>
> It is the lower nibble of this register. So 0xf.
>
> Take a look at:
>
> https://github.com/lunn/mv88e6xxx_dump/blob/master/mv88e6xxx_dump.c
>
Many thanks for the link; I will build and install it on the target.
Hope it will work with the older kernel (5.4.114) we're using.
> The 1 in 100f means it has found the PHY. But there is no link,
> 10/Half duplex, etc.
>
>> 1: 0003
>
> This at least looks sensible. Nothing is forced, normal speed
> detection should be performed. So what should happen is the link
> speed, duplex etc from the internal PHY should directly appear in
> register 0. There is no need for software to ask the PHY and then
> configure the MAC.
>
Ok, so the internal PHY seems to be configured as expected.
Does this mean that the issue is caused by the link partner?
I did notice that the RJ45 link LED on each of the peer devices no
longer light up. Previously, the LED was coming on. Perhaps it's time to
check the following:
- confirm the network cable for each link peer is good
- confirm each link peer works by connecting to a 100baseT or 1000baseT
switch
Thanks again for all of your feedback!
next prev parent reply other threads:[~2021-07-28 19:37 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-22 22:55 Dario Alcocer
2021-07-23 13:41 ` Andrew Lunn
2021-07-23 18:21 ` Dario Alcocer
2021-07-23 18:25 ` Andrew Lunn
2021-07-23 18:36 ` Dario Alcocer
2021-07-23 21:58 ` Dario Alcocer
2021-07-24 17:34 ` Andrew Lunn
2021-07-25 2:26 ` Dario Alcocer
2021-07-25 2:36 ` Dario Alcocer
2021-07-27 1:39 ` Dario Alcocer
2021-07-28 18:07 ` Dario Alcocer
2021-07-28 18:23 ` Andrew Lunn
2021-07-28 18:33 ` Dario Alcocer
2021-07-28 19:24 ` Andrew Lunn
2021-07-28 19:37 ` Dario Alcocer [this message]
2021-07-28 20:47 ` Andrew Lunn
2021-07-28 20:54 ` Dario Alcocer
2021-07-28 21:09 ` Andrew Lunn
2021-08-05 21:44 ` Dario Alcocer
2021-08-06 16:03 ` Dario Alcocer
2021-08-06 23:46 ` Dario Alcocer
2021-08-07 18:57 ` Andrew Lunn
2021-08-09 16:28 ` Dario Alcocer
2021-08-10 20:58 ` Dario Alcocer
2021-08-10 22:13 ` Andrew Lunn
2021-08-11 13:16 ` Dario Alcocer
2021-08-07 17:44 ` Andrew Lunn
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