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From: Dario Alcocer <dalcocer@helixd.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: netdev@vger.kernel.org
Subject: Re: Marvell switch port shows LOWERLAYERDOWN, ping fails
Date: Wed, 28 Jul 2021 11:33:35 -0700	[thread overview]
Message-ID: <59790fef-bf4a-17e5-4927-5f8d8a1645f7@helixd.com> (raw)
In-Reply-To: <YQGgvj2e7dqrHDCc@lunn.ch>

On 7/28/21 11:23 AM, Andrew Lunn wrote:
> On Wed, Jul 28, 2021 at 11:07:37AM -0700, Dario Alcocer wrote:
>> It appears the port link-state issue is caused by the mv88e6xxx switch
>> driver. The function mv88e6xxx_mac_config identifies the PHY as internal and
>> skips the call to mv88e6xxx_port_setup_mac.
>>
>> It does not make sense to me why internal PHY configuration should be
>> skipped.
> 
> The switch should do the configuration itself for internal PHYs. At
> least that works for other switches. What value does CMODE have for
> the port? 0xf?
> 
>      Andrew
> 

Is CMODE available via the DSA debugfs? Here are the registers for 
port0, which should be lan1:

root@dali:~# ls /sys/kernel/debug/dsa/switch0/
port0/        port1/        port2/        port3/        port4/ 
port5/        port6/        tag_protocol  tree
root@dali:~# ls /sys/kernel/debug/dsa/switch0/port0/
fdb    mdb    regs   stats  vlan
root@dali:~# cat /sys/kernel/debug/dsa/switch0/port0/regs
  0: 100f
  1: 0003
  2: 0000
  3: 1761
  4: 0433
  5: 0000
  6: 0010
  7: 0000
  8: 2080
  9: 0001
10: 0000
11: 0001
12: 0000
13: 0000
14: 0000
15: 9100
16: 0000
17: 0000
18: 0000
19: 0000
20: 0000
21: 0000
22: 0033
23: 0000
24: 3210
25: 7654
26: 0000
27: 8000
28: 0000
29: 0000
30: 0000
31: 0000
root@dali:~#

  reply	other threads:[~2021-07-28 18:33 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-22 22:55 Dario Alcocer
2021-07-23 13:41 ` Andrew Lunn
2021-07-23 18:21   ` Dario Alcocer
2021-07-23 18:25     ` Andrew Lunn
2021-07-23 18:36       ` Dario Alcocer
2021-07-23 21:58         ` Dario Alcocer
2021-07-24 17:34           ` Andrew Lunn
2021-07-25  2:26             ` Dario Alcocer
2021-07-25  2:36               ` Dario Alcocer
2021-07-27  1:39                 ` Dario Alcocer
2021-07-28 18:07                   ` Dario Alcocer
2021-07-28 18:23                     ` Andrew Lunn
2021-07-28 18:33                       ` Dario Alcocer [this message]
2021-07-28 19:24                         ` Andrew Lunn
2021-07-28 19:37                           ` Dario Alcocer
2021-07-28 20:47                             ` Andrew Lunn
2021-07-28 20:54                               ` Dario Alcocer
2021-07-28 21:09                             ` Andrew Lunn
2021-08-05 21:44                             ` Dario Alcocer
2021-08-06 16:03                               ` Dario Alcocer
2021-08-06 23:46                                 ` Dario Alcocer
2021-08-07 18:57                                   ` Andrew Lunn
2021-08-09 16:28                                     ` Dario Alcocer
2021-08-10 20:58                                       ` Dario Alcocer
2021-08-10 22:13                                         ` Andrew Lunn
2021-08-11 13:16                                           ` Dario Alcocer
2021-08-07 17:44                               ` Andrew Lunn

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