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From: Hayes Wang <hayeswang@realtek.com>
To: Heiner Kallweit <hkallweit1@gmail.com>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	nic_swsd <nic_swsd@realtek.com>,
	"koba.ko@canonical.com" <koba.ko@canonical.com>
Subject: RE: [PATCH net-next 2/2] r8169: change the L0/L1 entrance latencies for RTL8106e
Date: Sat, 7 Aug 2021 03:50:47 +0000	[thread overview]
Message-ID: <95d8ea6b2b814bb9932961360ccd2061@realtek.com> (raw)
In-Reply-To: <3cfd64a9-dff2-6e60-1524-ddbd1c388c01@gmail.com>

Heiner Kallweit <hkallweit1@gmail.com>
> Sent: Saturday, August 7, 2021 5:28 AM
[...]
> Most chip versions use rtl_set_def_aspm_entry_latency() that sets
> the value to 0x27. Does this value also work for RTL8106e?

No, it doesn't work.

> Can you explain how the L0 and L1 times in us map to the
> register value? Then we could add a function that doesn't work
> with a magic value but takes the L0 and L1 times in us as
> parameter.

L0 (bit 0~2):
	0: 1us
	1: 2us
	2: 3us
	3: 4us
	4: 5us
	5: 6us
	6: 7us
	7: 7us (The maximum is 7us)

L1 (bit 3~5):
	0: 1us
	1: 2us
	2: 4us
	3: 8us
	4: 16us
	5: 32us
	6: 64us
	7: 64us (The maximum is 64us)

Best Regards,
Hayes


  reply	other threads:[~2021-08-07  3:50 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-06  9:15 [PATCH net-next 0/2] r8169: adjust the setting " Hayes Wang
2021-08-06  9:15 ` [PATCH net-next 1/2] Revert "r8169: avoid link-up interrupt issue on RTL8106e if user enables ASPM" Hayes Wang
2021-08-06  9:15 ` [PATCH net-next 2/2] r8169: change the L0/L1 entrance latencies for RTL8106e Hayes Wang
2021-08-06 21:27   ` Heiner Kallweit
2021-08-07  3:50     ` Hayes Wang [this message]
2021-08-07  8:40 ` [PATCH net-next 0/2] r8169: adjust the setting " patchwork-bot+netdevbpf

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