Netdev Archive on lore.kernel.org help / color / mirror / Atom feed
From: Geert Uytterhoeven <geert@linux-m68k.org> To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>, Rob Herring <robh+dt@kernel.org>, Wolfgang Grandegger <wg@grandegger.com>, Marc Kleine-Budde <mkl@pengutronix.de>, "David S. Miller" <davem@davemloft.net>, Jakub Kicinski <kuba@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Philipp Zabel <p.zabel@pengutronix.de>, linux-can@vger.kernel.org, netdev <netdev@vger.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, linux-clk <linux-clk@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Linux-Renesas <linux-renesas-soc@vger.kernel.org>, Biju Das <biju.das.jz@bp.renesas.com> Subject: Re: [PATCH 3/6] dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock Date: Fri, 16 Jul 2021 10:56:23 +0200 [thread overview] Message-ID: <CAMuHMdWBqLcCGWkP9JoALuiXT1m9a1rRwR8ExShUQmJ1HCikZA@mail.gmail.com> (raw) In-Reply-To: <CA+V-a8v5m-F-n4E9HpwLe1C9gHWepTc0rCVk5oh5RCJ7oTXe2A@mail.gmail.com> Hi Prabhakar, On Fri, Jul 16, 2021 at 10:45 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Fri, Jul 16, 2021 at 9:08 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Thu, Jul 15, 2021 at 8:21 PM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > Add P0_DIV2 core clock required for CANFD module. CANFD core clock is > > > sourced from P0_DIV2 referenced from HW manual Rev.0.50. > > > > OK. > > > > > Also add R9A07G044_LAST_CORE_CLK entry to avoid changes in > > > r9a07g044-cpg.c file. > > > > I'm not so fond of adding this. Unlike the other definitions, it is > > not really part of the bindings, but merely a convenience definition > > for the driver. Furthermore it has to change when a new definition > > is ever added. > > > Agreed will drop this. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> > > > --- > > > include/dt-bindings/clock/r9a07g044-cpg.h | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h > > > index 0728ad07ff7a..2fd20db0b2f4 100644 > > > --- a/include/dt-bindings/clock/r9a07g044-cpg.h > > > +++ b/include/dt-bindings/clock/r9a07g044-cpg.h > > > @@ -30,6 +30,8 @@ > > > #define R9A07G044_CLK_P2 19 > > > #define R9A07G044_CLK_AT 20 > > > #define R9A07G044_OSCCLK 21 > > > +#define R9A07G044_CLK_P0_DIV2 22 > > > +#define R9A07G044_LAST_CORE_CLK 23 > > > > Third issue: off-by-one error, it should be 22 ;-) > > > 23 was intentionally as these numbers aren't used for core clock count > we use r9a07g044_core_clks[] instead. It ends up as an off-by-one bug in the range check in rzg2l_cpg_clk_src_twocell_get(). > Said that I'll drop this. OK. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
next prev parent reply other threads:[~2021-07-16 8:58 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-15 18:21 [PATCH 0/6] Renesas RZ/G2L CANFD support Lad Prabhakar 2021-07-15 18:21 ` [PATCH 1/6] dt-bindings: net: can: renesas,rcar-canfd: Document RZ/G2L SoC Lad Prabhakar 2021-07-16 7:38 ` Geert Uytterhoeven 2021-07-16 8:30 ` Lad, Prabhakar 2021-07-15 18:21 ` [PATCH 2/6] can: rcar_canfd: Add support for RZ/G2L family Lad Prabhakar 2021-07-16 7:47 ` Geert Uytterhoeven 2021-07-16 8:32 ` Lad, Prabhakar 2021-07-16 10:10 ` Marc Kleine-Budde 2021-07-15 18:21 ` [PATCH 3/6] dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock Lad Prabhakar 2021-07-16 8:07 ` Geert Uytterhoeven 2021-07-16 8:45 ` Lad, Prabhakar 2021-07-16 8:56 ` Geert Uytterhoeven [this message] 2021-07-16 9:02 ` Lad, Prabhakar 2021-07-15 18:21 ` [PATCH 4/6] clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0_DIV2 Lad Prabhakar 2021-07-16 8:09 ` Geert Uytterhoeven 2021-07-16 8:46 ` Lad, Prabhakar 2021-07-15 18:21 ` [PATCH 5/6] clk: renesas: r9a07g044-cpg: Add clock and reset entries for CANFD Lad Prabhakar 2021-07-16 7:55 ` Geert Uytterhoeven 2021-07-15 18:21 ` [PATCH 6/6] arm64: dts: renesas: r9a07g044: Add CANFD node Lad Prabhakar
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=CAMuHMdWBqLcCGWkP9JoALuiXT1m9a1rRwR8ExShUQmJ1HCikZA@mail.gmail.com \ --to=geert@linux-m68k.org \ --cc=biju.das.jz@bp.renesas.com \ --cc=davem@davemloft.net \ --cc=devicetree@vger.kernel.org \ --cc=kuba@kernel.org \ --cc=linux-can@vger.kernel.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-renesas-soc@vger.kernel.org \ --cc=mkl@pengutronix.de \ --cc=mturquette@baylibre.com \ --cc=netdev@vger.kernel.org \ --cc=p.zabel@pengutronix.de \ --cc=prabhakar.csengg@gmail.com \ --cc=prabhakar.mahadev-lad.rj@bp.renesas.com \ --cc=robh+dt@kernel.org \ --cc=sboyd@kernel.org \ --cc=wg@grandegger.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).