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From: Dario Alcocer <dalcocer@helixd.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: netdev@vger.kernel.org
Subject: Re: Marvell switch port shows LOWERLAYERDOWN, ping fails
Date: Mon, 9 Aug 2021 09:28:13 -0700	[thread overview]
Message-ID: <ac33ec5f-568e-e43c-5d58-48876a7d9b0d@helixd.com> (raw)
In-Reply-To: <YQ7Xo3UII/1Gw/G1@lunn.ch>

On 8/7/21 11:57 AM, Andrew Lunn wrote:
> On Fri, Aug 06, 2021 at 04:46:08PM -0700, Dario Alcocer wrote:
>> Any ideas on how to get ICMP working, using the DSA single-port
>> configuration example, are welcome.
> 
> Take a look at the port statistics. ethtool -S lan1 ? Do the counters
> show the packets being sent out? They are probably broadcast packets,
> ARP, not unicast ICMP.
> 
> Also ethtool -S eth0
> 
> At the end of the list, you see statistics for the CPU port.
> 
>     Andrew
> 

Andrew,

Well, I discovered that what I thought was physically lan1 was actually 
lan4, just as you had mentioned in an earlier message. :-)

The ping test is working now with the lan4 link peer.

However, I did notice something interesting in the output from 
mv88e6xxx_dump for the DSA ports. Apparently, the SERDES link between 
the two switch chips is not passing traffic, since no frames are 
received by either chip (note the "RX frame count" values below.) 
Interestingly, both DSA ports report link is up, but that may be because :

root@dali:~# mv88e6xxx_dump --port 4 --device mdio_bus/stmmac-0:1a
00 Port status                            0x1e0f
       Pause Enabled                        0
       My Pause                             0
       802.3 PHY Detected                   1
       Link Status                          Up
       Duplex                               Full
       Speed                                1000 Mbps
       EEE Enabled                          0
       Transmitter Paused                   0
       Flow Control                         0
       Config Mode                          0xf
01 Physical control                       0x003e
       RGMII Receive Timing Control         Default
       RGMII Transmit Timing Control        Default
       200 BASE Mode                        100
       Flow Control's Forced value          0
       Force Flow Control                   0
       Link's Forced value                  Up
       Force Link                           1
       Duplex's Forced value                Full
       Force Duplex                         1
       Force Speed                          1000 Mbps
...
04 Port control                           0x053f
       Source Address Filtering controls    Disabled
       Egress Mode                          Unmodified
       Ingress & Egress Header Mode         0
       IGMP and MLD Snooping                1
       Frame Mode                           DSA
...
13 RX frame count                         0x0000
...
root@dali:~# mv88e6xxx_dump --port 4 --device mdio_bus/stmmac-0:1e
00 Port status                            0x1e0f
       Pause Enabled                        0
       My Pause                             0
       802.3 PHY Detected                   1
       Link Status                          Up
       Duplex                               Full
       Speed                                1000 Mbps
       EEE Enabled                          0
       Transmitter Paused                   0
       Flow Control                         0
       Config Mode                          0xf
01 Physical control                       0x003e
       RGMII Receive Timing Control         Default
       RGMII Transmit Timing Control        Default
       200 BASE Mode                        100
       Flow Control's Forced value          0
       Force Flow Control                   0
       Link's Forced value                  Up
       Force Link                           1
       Duplex's Forced value                Full
       Force Duplex                         1
       Force Speed                          1000 Mbps
...
04 Port control                           0x053f
       Source Address Filtering controls    Disabled
       Egress Mode                          Unmodified
       Ingress & Egress Header Mode         0
       IGMP and MLD Snooping                1
       Frame Mode                           DSA
...
13 RX frame count                         0x0000
...

This probably explains why the none of the ports on the first chip 
(lan1, lan2, and lan3) work when running the ping test.

I will need to check with the hardware folks. The schematic indicates 
some DNP parts that may, in fact, have not been installed. ;-)


  reply	other threads:[~2021-08-09 16:28 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-22 22:55 Dario Alcocer
2021-07-23 13:41 ` Andrew Lunn
2021-07-23 18:21   ` Dario Alcocer
2021-07-23 18:25     ` Andrew Lunn
2021-07-23 18:36       ` Dario Alcocer
2021-07-23 21:58         ` Dario Alcocer
2021-07-24 17:34           ` Andrew Lunn
2021-07-25  2:26             ` Dario Alcocer
2021-07-25  2:36               ` Dario Alcocer
2021-07-27  1:39                 ` Dario Alcocer
2021-07-28 18:07                   ` Dario Alcocer
2021-07-28 18:23                     ` Andrew Lunn
2021-07-28 18:33                       ` Dario Alcocer
2021-07-28 19:24                         ` Andrew Lunn
2021-07-28 19:37                           ` Dario Alcocer
2021-07-28 20:47                             ` Andrew Lunn
2021-07-28 20:54                               ` Dario Alcocer
2021-07-28 21:09                             ` Andrew Lunn
2021-08-05 21:44                             ` Dario Alcocer
2021-08-06 16:03                               ` Dario Alcocer
2021-08-06 23:46                                 ` Dario Alcocer
2021-08-07 18:57                                   ` Andrew Lunn
2021-08-09 16:28                                     ` Dario Alcocer [this message]
2021-08-10 20:58                                       ` Dario Alcocer
2021-08-10 22:13                                         ` Andrew Lunn
2021-08-11 13:16                                           ` Dario Alcocer
2021-08-07 17:44                               ` Andrew Lunn

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